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Table of contents

Overview

Firmware for PCB-Master CPLD with designator U17. First CPLD Device in Chain: LCMX02-1200HC

Feature Summary

  • FMC VADJ Power
  • JTAG / FMC JTAG / PJTAG
  • RESET/Enable Management
  • LED
  • RGPIO
  • SD
  • CAN
  • USB
  • DisplayPort

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Schematic /Souce Code NameDirectionPinDescriptionPCB REV2 Exception
C_T1 24/ currently_not_usedNC
C_T2 26/ currently_not_usedNC
C_T3 25/ currently_not_usedNC
C_TCK         in131JTAG J28 (XMOD2) / FMC JTAG
 
C_TDI         in136JTAG J28 (XMOD2) / FMC JTAG 
C_TDO      out137JTAG J28 (XMOD2) / FMC JTAG 
C_TMS        in130JTAG J28 (XMOD2) / FMC JTAG 
CAN_FAULT    in106CAN 
CAN_RX       in107CAN 
CAN_S        out105CAN 
CAN_TX       out104CAN 
CLK_125MHZ / PHY_CLKin70/ currently_not_used 
CON_NTRST     117/ currently_not_used 
CON_RTCK / JTAG_RTCK    out125JTAG, Connector J30 
CON_SRST / JTAG_SRSTin127JTAG, Connector J30 
CON_TCK / JTAG_TCKin122JTAG, Connector J30 / PJTAG0 
CON_TDI / JTAG_TDIin119JTAG, Connector J30 / PJTAG0 
CON_TDO / JTAG_TDOout126JTAG, Connector J30 / PJTAG0 
CON_TMS / JTAG_TMSin121JTAG, Connector J30 / PJTAG0 
DIR_T1 23/ currently_not_usedNC
DIR_T2 28/ currently_not_usedNC
DIR_T3 27/ currently_not_usedNC
DP_AUX_DE   / DP_DE out92Display Port 
DP_AUX_RX   / DP_RXin91Display Port 
DP_AUX_TX    / DP_TXout93Display Port 
DP_EN        out77Display Port 
DP_TX_HPD  /DP_HDP in94Display Port 
ETH_RST      out62Ethernet 
EX_IO1        112PMOD / currently_not_used 
EX_IO2        113PMOD / currently_not_used 
EX_IO3        114PMOD / currently_not_used 
EX_IO4        115PMOD / currently_not_used 
F2_EN         19FAN J35 / currently_not_usedNC
F2PWM         20FAN J35 / currently_not_usedNC
F2SENSE       21FAN J35 / currently_not_usedNC
FMC_CLK_DIR  in73FMC 
FMC_TCK      out95FMC 
FMC_TDI      out96FMC 
FMC_TDO      in97FMC 
FMC_TMS      out98FMC 
FMC_VID0     out139FMC VADJ Power Selection 
FMC_VID1     out140FMC VADJ Power Selection 
FMC_VID2     out141FMC VADJ Power Selection 
GND 84REV03 unconnected / currently_not_usedUSB_TRST, other USB HUB
HDIO_SC10 / SC10 inout60FPGA / DP_RX or 'Z' 
HDIO_SC11 / SC11  in59FPGA / DP_DE 
HDIO_SC12 / SC12out58FPGA / DP_HPD 
HDIO_SC13 / SC13out57FPGA / RGPIO TX 
HDIO_SC14 / SC14  in56FPGA / RGPIO RX 
HDIO_SC15 / SC15in55FPGA / RGPIO CLK 
HDIO_SC16 / SC16   in54FPGA / CAN_S 
HDIO_SC17 / SC17in52FPGA / XMOD LED  
HDIO_SC18 / SC18in68FPGA / CAN_TX 
HDIO_SC19 / SC19out69FPGA / CAN_RX 
I2C_RST      out61I2C 
JTAGENB       120external Pin for CPLD Firmware Update  
LED_1A / JLED1out109USB3.0 LED Jellow 
LED_2A / JLED2Aout111USB3.0 LED Green/Orange 
LED_2B / JLED2Bout110USB3.0 LED Green/Orange 
MIO26        in41MIO / PJTAG 
MIO27        in40MIO / PJTAG 
MIO28        in39MIO  / PJTAG 
MIO29        in38MIO  / PJTAG 
OCLK_EN  / OSC_EN   out74Programmable Oscillator U45 
PHY_CONFIG   out65ETH PHY 
PHY_LED0     in67ETH PHY 
PHY_LED1     in86ETH PHY 
PHY_LED2     in85ETH PHY 
SC_CLK0 / CLK0    in76/ currently_not_usedSC_CLK_P
SC_CLK1 / CLK1    in75/ currently_not_usedSC_CLK_N
SC_IO0 / X0in50Master-Slave SC-Communication / Power Reset 
SC_IO1 / X1      in49Master-Slave SC-Communication / Power Reset 
SC_IO2 / X2in48Master-Slave SC-Communication / currently_not_used  
SC_IO3 / X3in47Master-Slave SC-Communication / currently_not_used 
SC_IO4  / X4    out45Master-Slave SC-Communication / SD WP to Slave CPLD  
SC_IO5 / X5     out44Master-Slave SC-Communication / currently_not_used 
SC_IO6 / X6out43Master-Slave SC-Communication / Sanity check to other CPLD (FMC VADJ Enable) 
SC_IO7 / X7out42Master-Slave SC-Communication / Sanity check to other CPLD (FMC VADJ Enable) 
SC_IO8        22Master-Slave SC-Communication / currently_not_usedNC
SC_SCL  / SCL    in14I2C Mux U27 / currently_not_used 
SC_SDA / SDA      in13I2C Mux U27 / currently_not_used 
SC2_SW3 / SW3    in6DIP-Switch S5-3 
SC2_SW4 / SW4    in5DIP-Switch S5-4 
SD_WP        in100MMC SD  
SFP_LED1 / SFP_LED0out81SFP 
SFP_LED2 / SFP_LED1out82SFP 
SFP_LED3 / SFP_LED2out78SFP 
SFP_LED4 / SFP_LED3out83SFP 
SFP1_LOS      32SFP / currently_not_usedNC, controlled by FPGA
SFP1_TX_DIS  out33SFPNC, controlled by FPGA
SFP2_LOS      35SFP / currently_not_usedNC, controlled by FPGA
SFP2_TX_DIS  out34SFPNC, controlled by FPGA
STAT_LED0 / LED0 99LED D4 Green  
STAT_LED1 / LED1 128LED D1 Red  
USB0_RST / USB_RST   out71USB (U9) PHY ResetUSB PHY and HUB Reset
USBH_LED_G3   11USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_G4   12USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_SS1  9USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_SS2 / dummyout133USB Hub (U4) Dummy Signal / currently_not_usedNC, other USB HUB
USBH_LED_SS3  132USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_SS4  138USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_MODE0   out142USB Hub (U4)NC, other USB HUB
USBH_MODE1   out143USB Hub (U4)NC, other USB HUB
USBH_RST     out10USB Hub (U4)NC, other USB HUB
XMOD1_A       3J28 (XMOD 2) / currently_not_used 
XMOD1_B       2J28 (XMOD 2) / currently_not_used 
XMOD1_E   /XMOD_E out4J28 (XMOD 2 LED) 
XMOD1_G / XMOD_G  in1J28 (XMOD 2 Button) 

 

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

FMC JTAG is connected to XMOD2 JTAG. Set DIP S4-3 to OFF for FMC access.

PJTAG (MIO29..26) is connected to JTAF Pinheader J30.

Power

FMC VADJ is 1.8V if S5-4 is ON else 1.2V.

Reset

Main Reset is send by Slave CPLD via X0, X1 Pins.

USB PHY hold ~0,6s after Main Reset or XMOD_G Reset or inv.RGPIO Bus Pin 0 (if active).

USB HUB hold ~0,25s after Main Reset or XMOD_G Reset or inv. RGPIO Bus Pin 0 (if active). Long delay is a BUGFIX: is currently need to start Linux before Reset is disabled.

I2C Reset is Main Reset  or inv. RGPIO Bus Pin 2 (if active).

ETH Reset is  Main Reset  or inv. RGPIO Bus Pin 3 (if active).

Enable

FMC VADJ Enable is set from Slave CPLD via Saity Check (X6, X7).

SFP1 and SFP2 are always enabled.

Oscillator U45 is enabled

USB

USB Hub Device Operation Mode (USBH_MODEx Pins) are set to internal ROM configuration. Can be controlled by RGPIO Bus Pin 4 and 5.

ETH

PHY Address is 1.

Display Port

SC10 is controlled by DP_RX when SC11 is zero else high impedance state. DP_TX controlled by SC10 and DP_DE controlled by SC11.SC12 is controlled by DP_HPD.

CAN

CAN_TX soured by SC18.

SC19 sourced by CAN_RX.

CAN_S sourced by S16.

SD

SD WP is forwarded to Slave CPLD.

RGPIO

RGPIO Pin to FPGAValue
0SW3
1SW4
2SD_WP
3XMOD_G
4'0'
5'0'
6'0'
7'0'
8CAN_FAULT
9PHY_LED0
10PHY_LED1
11PHY_LED2
12FMC_TDO
13FMC_CLKDIR
14JTAG_TRST
15JTAG_SRST
16'0'
17'0'
18'0'
19DP_HPD
20SDA
21SCL
22-23unused zero
24-27reserved
28-31Interface detection
RGPIO Pin from FPGAValue
0not USB_RST
1not USBH_RST
2not I2C_RST
3not ETH_RST
4not USBH_MODE0
5not USBH_MODE1
6LED0
7LED1
8SFP_LED0
9SFP_LED1
10SFP_LED2
11SFP_LED3
12JLED1
13JLED2A
14JLED2B
15-23unused
24-27reserved
28-31Interface detection

 

LED

NameDescription
LED0 D4 GreenRGPIO (6) when active else USB HUB RSTN
LED1 D1 RedRGPIO (7) when active else Main Reset from Slave CPLD
SFP_LED0 RedRGPIO (8) when active else blinking when PCB power is on and reset Button is pressed else off
SFP_LED1 GreenRGPIO (9) when active else blinking when PCB power is on and reset Button is pressed else off
SFP_LED2 RedRGPIO (10) when active else blinking when PCB power is on and reset Button is pressed else off
SFP_LED3 GreenRGPIO (11) when active else blinking when PCB power is on and reset Button is pressed else off
JLED1 YellowRGPIO (12) when active else blinking when PCB power is on and reset Button is pressed else not PHY_LED0 when X1 is zero else off
JLED2A GreenRGPIO (13) when active else blinking when PCB power is on and reset Button is pressed else not PHY_LED1 when X1 is zero else on
JLED2B OrangeRGPIO (14) when active else blinking when PCB power is on and reset Button is pressed else off
XMOD_E RedBlinking when Main Power Reset else SC17

*Blinking: ~1,5Hz

Appx. A: Change History

Revision Changes

CPLD REV05 to REV06

  • BUGFIX: renamed SC19 to SC17
  • Connect FMC JTAG to XMOD2 JTAG
  • Connect PJTAG0 (MIO29..26) to JTAG Pin Header J30
  • Connect CAN to PL
  • RGPIO Pin changes

CPLD REV04 to REV05

  • SD WP
  • XMOD LED access over PL

Older Revision (PCB REV03) to CPLD REV04

  • Fix USB HUB Mode default state over RGPIO
  • Invert JLED2B over RGPIO

Older Revision (PCB REV02) to CPLD REV04

  • Add all functionality from older Revision (PCB REV03)

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV06(REV02 Special Firmware!), REV03,REV04
  • small Update Pinout Table
2017-10-18

v.25

REV06(REV02 Special Firmware!), REV03,REV04John Hartfiel
  • Revision  06 finished

2017-06-20

v.23

REV05(REV02 Special Firmware!), REV03,REV04John Hartfiel
  • Document Bugfix, XMOD LED is connected to SC17
2017-06-12v.22REV05(REV02 Special Firmware!), REV03,REV04John Hartfiel
  • Port description update
2017-06-09v.21REV05(REV02 Special Firmware!), REV03,REV04John Hartfiel
  • Revision  05 finished
2017-06-08v.17REV04(REV02 Special Firmware!), REV03,REV04John Hartfiel
  • document style update
2017-03-10v.15REV04(REV02 Special Firmware!), REV03,REV04John Hartfiel
  • Revision 04 finished
2016-12-14

v.1

--- 
  • Initial release
 All   

Appx. B: Legal Notices

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Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Copyright Notice

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Technology Licenses

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REACH, RoHS and WEEE

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WEEE

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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