Trenz Electronic use different memory types for Trenz Ultrascale+ Modules. Following 8 Gbit memory types are equivalent and can be used with the identical memory timing settings:
| Manufacturer | Device Name | Article Name Identification Code(1) |
|---|---|---|
| Samsung | K4A8G165WB-BIRC | 2 |
K4A8G165WC-BITDTCV | 8 | |
| Nanya | NT5AD512M16H4-JRI | 5 |
| ISSI | IS43QR16512A-075VBLI | 6 |
(1) assembled memory can be identified by their article name according to encoding table on Digit/Letter at position 14, see:
Recommended Zynq MP PS Memory Configuration
| Interface | 64 Bit without ECC (4 device x16) | 64 Bit with ECC (5 device x16) | 32 Bit without ECC (2 device x16) |
|---|---|---|---|
| Series |
|
|
|
| Total DDR Size | 4 GByte | 4 GByte+1 GByte ECC | 2 GByte |
| interface configuration | |||
| effective DRAM width | 64 Bit | 32 Bit | |
| ECC | disabled | enabled | disabled |
| DRAM I2C Bus per die | 16 Bit | ||
| DRAM Device Capacity per Die | 8192 MBits | ||
| Bank Group Address Count (Bits) | 1 | ||
| Bank Address Count(Bits) | 2 | ||
| Row Address Count (Bits) | 16 | ||
| Column Address Count(Bits) | 10 | ||
| Dual Rank | disabled | ||
| timing configuration | |||
| Device Frequency | 2400 | ||
| CAS Latency (nCL) | 17 | ||
| RAS to CAS Delay (nRCD) | 17 | ||
| Precharge Time (nRP) | 17 | ||
| Cas Write Latency (CWL) | 16 | ||
| tRC(Row Cycle Time) (=tRAS+tRP) | 46.161 | ||
| tRASmin | 32.0 | ||
| tFAW | 30 | ||
| additional Latency(cycles) | 0 | ||
| other configuration | |||
| Memory Address Map | ROW BANK COL | ||
| Data Mask and DBI | DM NO DBI | ||
| Address Mirroring | disabled | ||
| 2nd CLK | disabled | ||
| Parity | disabled | ||
| 2tCK Command | disabled | ||
| Power Down | disabled | ||
| Clock Stop | disabled | ||
| Low-Power Auto Self-Refresh | manual normal | ||
| Temp Controlled Refresh | enabled | ||
| Max Operating Temp. | Normal | ||
| Fine Granularity Refresh Mode | 1x | ||
| Self Refresh Abort | disabled | ||
Maximum speed is limited of 2400MBit/s according ZynqMP datasheet (ds925) for single rank components on FFVC900, FBVB900 and SFVC784 package.
The following data sheets were used to verify timing configuration:
Samsung:
- 8G_C_DDR4_Samsung_Spec_REV1.31 Apr.17.pdf
- Version 1.31
- K4A8G045WC Datasheet (for Commercial)
- K4A8G165WB_BC_I_Rev1_6-1.pdf Jun.16
- Version 1.6
Nanya:
- 8Gb_DDR4_H_Die_component_Datasheet.pdf
- "DDR4-8Gb H-Die NT5AD2048M4H3/NT5AD1024M8H3/NT5AD512M16H4"
- Version 1.4 08/2025
ISSI:
- 43-46QR81024A-16512A.pdf
- "IS43/46QR81024A/IS43/46QR16512A"
- Version: REV.I 06/20/2025
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