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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
   
   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see alsoTE Board Part Files
5. Create XSA and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Generate Programming Files with Vitis
   
   1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
      App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
7. Copy Application (memory_test.elf) into \firmware\microblaze_0\microblaze_0\
   1. memory_test.elf or srec_spi_bootloader.elf
      Note only one elf shouldbe put into this folder
8. Regenerate Design:
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
   2. (alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.

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1. Connect JTAG and power on PCB
2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
3. Open Vivado HW Manager
4. Program Bitfile
   1. Note: Flash musst be configured with correct mcs file, in case srec_spi_bootloader.elf is used as app

Usage

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1. Open Serial Console (e.g. putty)
   
   1. Speed: 9600
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Uart Console:
   Xilinx Memory test on HyperRAM
   Image RemovedSrec and Hello TE0725: Important, Hello TE0725 is running on Hyperam and Hyperram DEMO-IP has timebomb and stop working after appr. 10 min
   Image Added
   

System Design - Vivado

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