MicroBlaze Design with 10 minutes HyperRAM memory test example.
This reference design is bundled with a FREE evaluation edition of the low-cost, commercially proven, high performance memory controller IP supplied by Synaptic Laboratories Ltd (SLL). This free IP evaluation license never expires, and no customer registration or NIC ID is required. Click here to find the latest free trials of SLL’s memory controller IP for HyperBus, OctaBus, Xccela Bus, JEDEC xSPI Profile 1.0 and JEDEC xSPI Profile 2.0 for Intel, Microchip, and Xilinx FPGA. SLL IP is also qualified for use with Trenz HS CRUVI enabled boards. Please send all sales enquiry and technical support questions for SLL’s IP to email@example.com
Refer to http://trenz.org/te0725-info for the current online version of this manual and other available documentation.
- Vivado/Vitis 2021.2
- S/Labs HBMC IP (Free Trail IP)
Release Notes and Know Issues
|Issues||Description||Workaround||To be fixed version|
|No known issues||---||---||---|
|Vitis||2021.2||needed, Vivado is included into Vitis installation|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
|Module Model||Board Part Short Name||PCB Revision Support||DDR||QSPI Flash||EMMC||Others||Notes|
|TE0725-03-100-2CF||100_2c||REV03|REV02|REV01||NA||32MB||NA||8MB HypeRAM||POF assembled|
*used as reference
Design supports following carriers:
Additional HW Requirements:
|TE0790 JTAG Programmer||It's not recommended to use TE0790 for power supply( TE0790 TRM#PowerandPower-OnSequence)|
|External power supply|
For general structure and of the reference design, see Project Delivery - Xilinx devices
|Vivado Project will be generated by TE Scripts|
|Vitis||<project folder>\sw_lib||Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation|
|BIT-File||*.bit||FPGA (PL Part) Configuration File|
|DebugProbes-File||*.ltx||Definition File for Vivado/Vivado Labtools Debugging Interface|
|Diverse Reports||---||Report files in different formats|
|Hardware-Platform-Specification-Files||*.xsa||Exported Vivado Hardware Specification for Vitis and PetaLinux|
|LabTools Project-File||*.lpr||Vivado Labtools Project File|
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
|Software-Application-File||*.elf||Software Application for Zynq or MicroBlaze Processor Systems|
Converted Software Application for MicroBlaze Processor Systems
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
- Xilinx Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Using Vivado GUI is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf
manually on Vivado
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
(optional) Copy Application (spi_bootloader.elf) from prebuilt-folder into \firmware\microblaze_0\ and regenerate design with
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Press the reset button to start the application and see the output in the console
Not used on this Example.
- Connect JTAG and power on PCB
- Open Vivado HW Manager
- Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"
HBMC IP is a 10 minute run-time limited evaluation version of the full-edition
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- boot process
1. FPGA Loads Bitfile from Flash
3. Hello Trenz will be run on UART console.
info: Do not reboot, if Bitfile programming over JTAG is used as programming method.
Open Serial Console (e.g. putty) Hello TE0725 will run on endless loop.
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Power On PCB (Do not restart, if you use Bitfile programming)
System Design - Vivado
Basic module constraints
Design specific constraints
Software Design - Vitis
For SDK project creation, follow instructions from:
Template location: ./sw_lib/sw_apps/
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the hello_te0725.elf from QSPI-Flash to RAM. Hence *.srec becomes redundant.
- Modified Files: bootloader.c
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
Hello TE0725 is a Xilinx Hello World example as endless loop instead of one single console output.
Xilinx default memory test.
No additional software is needed.
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