Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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MicroBlaze Design with 10 minutes HyperRAM memory test example.
This reference design is bundled with a FREE evaluation edition of the low-cost, commercially proven, high performance memory controller IP supplied by Synaptic Laboratories Ltd (SLL). This free IP evaluation license never expires, and no customer registration or NIC ID is required. Click here to find the latest free trials of SLL’s memory controller IP for HyperBus, OctaBus, Xccela Bus, JEDEC xSPI Profile 1.0 and JEDEC xSPI Profile 2.0 for Intel, Microchip, and Xilinx FPGA. SLL IP is also qualified for use with Trenz HS CRUVI enabled boards. Please send all sales enquiry and technical support questions for SLL’s IP to info@synaptic-labs.com
Refer to http://trenz.org/te0725-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
*used as reference |
Design supports following carriers:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
(optional) Copy Application (spi_bootloader.elf) from prebuilt-folder into \firmware\microblaze_0\ and regenerate design with
TE::hw_build_design -export_prebuilt |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp hello_te0725 |
Not used on this Example.
HBMC IP is a 10 minute run-time limited evaluation version of the full-edition |
1. FPGA Loads Bitfile from Flash 3. Hello Trenz will be run on UART console. info: Do not reboot, if Bitfile programming over JTAG is used as programming method.
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property PACKAGE_PIN A13 [get_ports HB_CLK0_0] set_property PACKAGE_PIN A14 [get_ports HB_CLK0n_0] set_property PACKAGE_PIN E17 [get_ports {HB_dq_0[0]}] set_property PACKAGE_PIN B17 [get_ports {HB_dq_0[1]}] set_property PACKAGE_PIN F18 [get_ports {HB_dq_0[2]}] set_property PACKAGE_PIN F16 [get_ports {HB_dq_0[3]}] set_property PACKAGE_PIN G17 [get_ports {HB_dq_0[4]}] set_property PACKAGE_PIN D18 [get_ports {HB_dq_0[5]}] set_property PACKAGE_PIN B18 [get_ports {HB_dq_0[6]}] set_property PACKAGE_PIN A16 [get_ports {HB_dq_0[7]}] set_property PACKAGE_PIN E18 [get_ports HB_RWDS_0] set_property PACKAGE_PIN D17 [get_ports HB_CS1n_0] set_property PACKAGE_PIN J17 [get_ports HB_RSTn_0] #set_property PACKAGE_PIN A18 [get_ports HB_CS0n_0 ] #set_property PACKAGE_PIN J18 [get_ports HB_INTn_0 ] #set_property PACKAGE_PIN C17 [get_ports HB_RSTOn_0] # # FPGA Pin Voltage assignment # set_property IOSTANDARD LVCMOS18 [get_ports HB_CLK0_0] set_property IOSTANDARD LVCMOS18 [get_ports HB_CLK0n_0] set_property IOSTANDARD LVCMOS18 [get_ports {HB_dq_0[*]}] set_property IOSTANDARD LVCMOS18 [get_ports HB_CS1n_0] set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTn_0] set_property IOSTANDARD LVCMOS18 [get_ports HB_RWDS_0] #set_property IOSTANDARD LVCMOS18 [get_ports HB_CS0n_0] #set_property IOSTANDARD LVCMOS18 [get_ports HB_INTn_0] #set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTOn_0] #set_property PULLUP true [get_ports HB_RSTOn_0] #set_property PULLUP true [get_ports HB_INTn_0] # #Hyperbus Clock - change according to clk pin on PLL # create_generated_clock -name clk_0 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0] create_generated_clock -name clk_90 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT1] create_generated_clock -name clk_180 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT2] # #100Mhz clock freqeuncy - change accordingly # set hbus_freq_ns 10 set dqs_in_min_dly -0.5 set dqs_in_max_dly 0.5 set HB_dq_ports [get_ports HB_dq_0[*]] # #Create RDS clock and RDS virtual clock # create_clock -period $hbus_freq_ns -name rwds_clk [get_ports HB_RWDS_0] create_clock -period $hbus_freq_ns -name virt_rwds_clk # #Input Delay Constraint - HB_RWDS-HB_DQ # set_input_delay -clock [get_clocks virt_rwds_clk] -max ${dqs_in_max_dly} ${HB_dq_ports} set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -max ${dqs_in_max_dly} ${HB_dq_ports} -add_delay set_input_delay -clock [get_clocks virt_rwds_clk] -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay set_multicycle_path -setup -end -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] 0 set_multicycle_path -setup -end -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] 0 set_false_path -fall_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -setup set_false_path -rise_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -setup set_false_path -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -hold set_false_path -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -hold set_false_path -from [get_clocks clk_0] -to [get_clocks rwds_clk] set_false_path -from [get_clocks rwds_clk] -to [get_clocks clk_0] # #Output Delay Constraint - HB_CLK0-HB_DQ # create_generated_clock -name HB_CLK0_0 -source [get_pins */*/*/U_IO/U_CLK0/dq_idx_[0].ODDR_inst/C] -multiply_by 1 -invert [get_ports HB_CLK0_0] set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports} set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports} set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports} -clock_fall -add_delay set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports} -clock_fall -add_delay set_false_path -from [get_pins */*/*/U_HBC/*/dq_io_tri_reg/C] -to ${HB_dq_ports} set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_1_reg/CLR] set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_2_reg/CLR] set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_3_reg/CLR] set_false_path -from [get_clocks rwds_clk] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_1/inst/mmcm_adv_inst/CLKOUT0]] set_false_path -from [get_clocks virt_rwds_clk] -to [get_clocks rwds_clk] |
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For SDK project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the hello_te0725.elf from QSPI-Flash to RAM. Hence *.srec becomes redundant.
Descriptions:
Hello TE0725 is a Xilinx Hello World example as endless loop instead of one single console output.
Xilinx default memory test.
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No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
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