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Scroll Title |
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anchor | Table_OBP_USB |
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title | General Overview of the USB PHY Signals |
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orientation | portrait |
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sortDirection | ASC |
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PHY Pin | Connected to | B2B | Notes |
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DP - 18, | OTG-D_P | JM3 - 47 | USB data line | DM - 19 | OTG-D_N | JM3 - 49 | USB data line | CPEN - 17 | VBUS_EN | JM3 - 53 | External USB power switch | VBUS - 22 | VBUS | JM3 - 55 |
| ID - 23 | ID | JM3 - 51 |
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Test Points
Scroll Title |
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anchor | Table_OBP_TestPoints |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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Test Point | Signal | Connected to | Notes |
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1 |
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| 3 |
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On-board Peripherals
Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Power supply with minimum current capability of xx 3 A for system startup is recommended.
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Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* | 3.3VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin |
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B2B ConnectorJM3 Pin |
Bank Voltages
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board | 3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board | 3.3VIN | - | 91 | Output | JTAG reference voltage | +1.8V | 39 | - | Output | Internal +1.8V voltage level | VCCIOB | - | 1, 3 | Input | General purpose I/O bank voltage | VCCIOD | - | 7, 9 | Input | High speed I/O bank voltage (max. +1.8 V) | +3.3V | - | 10, 12 | Output | Internal +3.3 V voltage level |
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Bank Voltages
Scroll Title |
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anchor | Table_PWR_BV |
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title | Zynq Polarfire SoC bank voltages. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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Bank 0 HSIO | VCCIOD | Variable | max. voltage +1.8 V | Bank 1 GPIO | VCCIOB | Variable | max. voltage +3.3 V | Bank 2 MSSIO | +3.3V | +3.3 V |
| Bank 3 | +1.8V | +1 |
.8 V |
| Bank 4 MSSIO | +3.3V | +3.3 V |
| Bank 5 | +3.3V | +3.3 V |
| Bank 6 MSS DDR | +1.1V_LPDDR4 | +1.1 V |
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sortEnabled | false |
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cellHighlighting | true |
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Board to Board Connectors
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Scroll Title |
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anchor | Table_TS_AMR |
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title | PS absolute Absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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VIN | Supply voltage | -0.3 | 6.0 | V | 3.3VIN | Supply voltage | -0.3 | 3.6 | V | VCCIOB | I/O bank voltage | -0.5 | 3.6 | VV | VCCIOD | I/O bank voltage | -0.5 | 2.0 |
V | V | V | V
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Recommended Operating Conditions
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Scroll Title |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN |
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| V | See ???? datasheets. | V | See Xilinx ???? datasheet.3.3VIN |
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| V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. VCCIOB |
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| V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | VCCIOD |
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| V | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. |
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Physical Dimensions
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