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Template Revision 2.9 - on construction3.0 Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" - Changes Change List 2.8 9 to 23.90
- add fix table of content
- repace add table html with macrosize as macro
- removed page initial creator
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
Zynq PS Design with Linux Example and Camera Demo.
Refer to http://trenz.org/te0727-info for the current online version of this manual and other available documentation.
Key Features
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Notes : - Add basic key futures, which can be tested with the design
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Excerpt |
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- Vitis/Vivado 2019.2
- RPI Camera 1.3 or 2.1
- HDMI
- PetaLinux
- SD
- USB
- I2C
- Special FSBL for QSPI programming
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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anchor | Table_DRH |
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title | Design Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Vivado | Project Built | Authors | Description |
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2020-11-24 | | TE0727-zbzerodemo1_noprebuilt-vivado_2019.2-build_15_20201124064113.zip TE0727-zbzerodemo1-vivado_2019.2-build_15_20201124064045.zip | Oleksandr Kiyenko/ John Hartfiel
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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anchor | Table_KI |
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title | Known Issues |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Issues | Description | Workaround | To be fixed version |
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init.sh | automatically camera selection failed | select camera manually on init.sg | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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anchor | Table_SW |
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title | Software |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Software | Version | Note |
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Vitis | 2019.2 | needed,Vivado is included into Vitis installation | PetaLinux | 2019.2 | needed |
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Hardware
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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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anchor | Table_HWM |
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title | Hardware Modules |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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TE0727-01-010-1C | 10_512MB | REV01 | 512MB DDR3L | 16MB |
| small design modification needed (I2C for camera) | TE0727-02-41C34 | 10_512MB | REV01 | 512MB DDR3L | 16MB |
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Design supports following carriers:
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anchor | Table_HWC |
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title | Hardware Carrier |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional HW Requirements:
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anchor | Table_AHW |
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title | Additional Hardware |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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USB Power | Use USB2.0 or higher for power supply via USB | USB Cable | Connect to USB2 or better USB3 Hub for proper power supply over USB | Raspberry Pi Camera Rev 1.3 or Camera Rev 2.1 |
| Monitor | DELL Model Number: U2412M | HDMI Cable | -- | HDMI to Mini HTMI adapter |
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Content
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Notes : - the content of the zip file
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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anchor | Table_DS |
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title | Design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
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anchor | Table_ADS |
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title | Additional design sources |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Location | Notes |
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init.sh | <design name>/misc/init_script | Additional Initialization Script for Linux (used to enable camera) |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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anchor | Table_PF |
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title | Prebuilt files |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- For 128MB and 64MB only:Netboot Offset must be reduced manually, see 69107715
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<DDR size>", if exist, otherwise "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
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Note: - Programming and Startup procedure
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on the carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
optional "TE::pr_program_flash -swapp hello_te0726" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Important: Do not copy Boot.bin on SD(is not used see SD note), only other files.
- Copy init.sh on SD-Card
- location: <design_name>/misc/sd/
- Insert SD-Card
SD
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (u-boot)
JTAG
Not used on this Example.
Usage
- Prepare HW like described in section 69107715
- Connect UART USB (most cases same as JTAG)
- Insert SD Card with image.ub
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use a Linux shell now.
- I2C 1 Bus type: i2cdetect -y -r 5
Bus 0...5 possible - USB: insert USB device
- Camera stream will be enabled via init.sh script on SD
- Take image from camera (must be enabled with init.sh scripts):
- write image to webserver: fbgrab -d /dev/fb1 /srv/www/camera.png
- Display image on host PC: http://<ZynqBerry IP>/camera.png
System Design - Vivado
Block Design
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anchor | Figure_BD |
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title | Block Design |
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PS Interfaces
Activated interfaces:
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anchor | Table_PSI |
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title | PS Interfaces |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Note |
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DDR | --- | QSPI | MIO | USB0 | MIO, | SD1 | MIO | UART1 | MIO | I2C0 | EMIO | I2C1 | MIO | GPIO | MIO / EMIO | USB RST | MIO | TTC0..1 | MIO | WDT | MIO | AXI HP0..1 |
| DMA0..1 |
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Constraints
Basic module constraints
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language | ruby |
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title | _i_bitgen_common.xdc |
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#
# Common BITGEN related settings for TE0727 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design] |
Design specific constraint
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language | ruby |
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title | _i_common.xdc |
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#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
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language | ruby |
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title | _i_te0727.xdc |
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set_property PACKAGE_PIN G11 [get_ports {CEC_A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CEC_A[0]}]
set_property PACKAGE_PIN H13 [get_ports {HPD_A}]
set_property IOSTANDARD LVCMOS33 [get_ports {HPD_A}]
set_property PACKAGE_PIN G14 [get_ports {GLED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GLED[0]}]
set_property PACKAGE_PIN G12 [get_ports {IIC_A_scl_io}]
set_property PACKAGE_PIN H12 [get_ports {IIC_A_sda_io}]
set_property IOSTANDARD LVCMOS33 [get_ports {IIC_A_*}]
set_property PACKAGE_PIN K12 [get_ports {CT_HPD[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {CT_HPD[0]}]
set_property PACKAGE_PIN F12 [get_ports {HDMI_TXC_P}]
set_property PACKAGE_PIN E13 [get_ports {HDMI_TXC_N}]
set_property PACKAGE_PIN E11 [get_ports {HDMI_TX_P[0]}]
set_property PACKAGE_PIN E12 [get_ports {HDMI_TX_N[0]}]
set_property PACKAGE_PIN G15 [get_ports {HDMI_TX_P[1]}]
set_property PACKAGE_PIN F15 [get_ports {HDMI_TX_N[1]}]
set_property PACKAGE_PIN F14 [get_ports {HDMI_TX_N[2]}]
set_property PACKAGE_PIN F13 [get_ports {HDMI_TX_P[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {HDMI_*}]
set_property PACKAGE_PIN J11 [get_ports {GPIO_tri_io[0]}]
set_property PACKAGE_PIN H11 [get_ports {GPIO_tri_io[1]}]
set_property PACKAGE_PIN J15 [get_ports {GPIO_tri_io[2]}]
set_property PACKAGE_PIN L15 [get_ports {GPIO_tri_io[3]}]
set_property PACKAGE_PIN N13 [get_ports {GPIO_tri_io[4]}]
set_property PACKAGE_PIN P8 [get_ports {GPIO_tri_io[5]}]
set_property PACKAGE_PIN M10 [get_ports {GPIO_tri_io[6]}]
set_property PACKAGE_PIN L12 [get_ports {GPIO_tri_io[7]}]
set_property PACKAGE_PIN M11 [get_ports {GPIO_tri_io[8]}]
set_property PACKAGE_PIN P10 [get_ports {GPIO_tri_io[9]}]
set_property PACKAGE_PIN P9 [get_ports {GPIO_tri_io[10]}]
set_property PACKAGE_PIN K15 [get_ports {GPIO_tri_io[11]}]
set_property PACKAGE_PIN M9 [get_ports {GPIO_tri_io[12]}]
set_property PACKAGE_PIN L13 [get_ports {GPIO_tri_io[13]}]
set_property PACKAGE_PIN L14 [get_ports {GPIO_tri_io[14]}]
set_property PACKAGE_PIN M15 [get_ports {GPIO_tri_io[15]}]
set_property PACKAGE_PIN J14 [get_ports {GPIO_tri_io[16]}]
set_property PACKAGE_PIN N14 [get_ports {GPIO_tri_io[17]}]
set_property PACKAGE_PIN K11 [get_ports {GPIO_tri_io[18]}]
set_property PACKAGE_PIN N9 [get_ports {GPIO_tri_io[19]}]
set_property PACKAGE_PIN J13 [get_ports {GPIO_tri_io[20]}]
set_property PACKAGE_PIN H14 [get_ports {GPIO_tri_io[21]}]
set_property PACKAGE_PIN R10 [get_ports {GPIO_tri_io[22]}]
set_property PACKAGE_PIN M14 [get_ports {GPIO_tri_io[23]}]
set_property PACKAGE_PIN P15 [get_ports {GPIO_tri_io[24]}]
set_property PACKAGE_PIN M12 [get_ports {GPIO_tri_io[25]}]
set_property PACKAGE_PIN K13 [get_ports {GPIO_tri_io[26]}]
set_property PACKAGE_PIN R15 [get_ports {GPIO_tri_io[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_io*}]
set_property PACKAGE_PIN N12 [get_ports {CSI_C_N}]
set_property PACKAGE_PIN N11 [get_ports {CSI_C_P}]
set_property PACKAGE_PIN R8 [get_ports {CSI_D_N[0]}]
set_property PACKAGE_PIN R7 [get_ports {CSI_D_P[0]}]
set_property PACKAGE_PIN R13 [get_ports {CSI_D_N[1]}]
set_property PACKAGE_PIN R12 [get_ports {CSI_D_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CSI_*}]
set_property PACKAGE_PIN N8 [get_ports {CLP_D_N[0]}]
set_property PACKAGE_PIN N7 [get_ports {CLP_D_P[0]}]
set_property PACKAGE_PIN P14 [get_ports {CLP_D_N[1]}]
set_property PACKAGE_PIN P13 [get_ports {CLP_D_P[1]}]
#set_property PACKAGE_PIN R11 [get_ports {CLP_C_N}]
#set_property PACKAGE_PIN P11 [get_ports {CLP_C_P}]
set_property IOSTANDARD HSUL_12 [get_ports {CLP_*}]
set_property PULLDOWN true [get_ports {CLP_*}]
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
create_clock -period 6.250 -name csi_clk -add [get_ports CSI_C_P]
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Software Design - Vitis
For SDK project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2018.3 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2018.3 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
SDK Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2019.2 FSBL
General:
Module Specific:
- Add Files: all TE Files start with te_*
- enable VTC and VDMA cores for camera access
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0727
Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
U-Boot
Start with petalinux-config -c u-boot
Changes:
Device Tree
Code Block |
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/include/ "system-conf.dtsi"
/ {
};
/ {
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
// HDMI Output frame buffer
hdmi_fb_reserved_region@1FC00000 {
compatible = "removed-dma-pool";
no-map;
// 512M (M modules)
reg = <0x1FC00000 0x400000>;
// 128M (R modules)
//reg = <0x7C00000 0x400000>;
};
/* // Use second frame buffer if you want separate area for camera image
camera_fb_reserved_region@1FC00000 {
compatible = "removed-dma-pool";
no-map;
// 512M (M modules)
reg = <0x1FC00000 0x400000>;
// 128M (R modules)
//reg = <0x7800000 0x400000>;
};
*/
};
hdmi_fb: framebuffer@0x1FC00000 { // HDMI out
compatible = "simple-framebuffer";
// 512M (M modules)
reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
// 128M (R modules)
//reg = <0x7C00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
status = "okay";
};
/* // In "go through" mode only one framebuffer is used
camera_fb: framebuffer@0x1FC00000 { // CAMERA in
compatible = "simple-framebuffer";
// 512M (M modules)
reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
// 128M (R modules)
//reg = <0x7800000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
*/
vcc_3V3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vccaux-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
partition@0x00000000 {
label = "boot";
reg = <0x00000000 0x00500000>;
};
partition@0x00500000 {
label = "bootenv";
reg = <0x00500000 0x00020000>;
};
partition@0x00520000 {
label = "kernel";
reg = <0x00520000 0x00a80000>;
};
partition@0x00fa0000 {
label = "spare";
reg = <0x00fa0000 0x00000000>;
};
};
};
/*
* We need to disable Linux VDMA driver as VDMA
* already configured in FSBL
*/
&video_out_axi_vdma_0 {
// Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL)
status = "disabled";
// Solution 2: Configure VDMA using the custom driver (VDMA configuration in FSBL should be disabled)
//compatible = "trenz,vdmafb";
//width = <1280>;
//height = <720>;
//stride = <(1280 * 4)>;
//format = "a8b8g8r8";
};
&video_in_axi_vdma_0 {
// Solution 1: Disable satandard VDMA driver (VDMA configuration should be done in the FSBL)
status = "disabled";
};
&gpio0 {
interrupt-controller;
#interrupt-cells = <2>;
};
/* I2C1 */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
i2cmux: i2cmux@70 {
compatible = "nxp,pca9540";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
ID_I2C@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
CSI_I2C@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
/* USB */
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
usb-phy = <&usb_phy0>;
} ;
|
Kernel
Start with petalinux-config -c kernel
Changes:
- CONFIG_MII=y
- CONFIG_XILINX_GMII2RGMII=y
- CONFIG_USB_USBNET=y
- CONFIG_USB_NET_AX8817X=y
- CONFIG_USB_NET_AX88179_178A=y
- CONFIG_USB_NET_CDCETHER=y
- # CONFIG_USB_NET_CDC_EEM is not set
- CONFIG_USB_NET_CDC_NCM=y
- # CONFIG_USB_NET_HUAWEI_CDC_NCM is not set
- # CONFIG_USB_NET_CDC_MBIM is not set
- # CONFIG_USB_NET_DM9601 is not set
- # CONFIG_USB_NET_SR9700 is not set
- # CONFIG_USB_NET_SR9800 is not set
- # CONFIG_USB_NET_SMSC75XX is not set
- CONFIG_USB_NET_SMSC95XX=y
- # CONFIG_USB_NET_GL620A is not set
- CONFIG_USB_NET_NET1080=y
- # CONFIG_USB_NET_PLUSB is not set
- # CONFIG_USB_NET_MCS7830 is not set
- # CONFIG_USB_NET_RNDIS_HOST is not set
- CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
- CONFIG_USB_NET_CDC_SUBSET=y
- # CONFIG_USB_ALI_M5632 is not set
- # CONFIG_USB_AN2720 is not set
- CONFIG_USB_BELKIN=y
- CONFIG_USB_ARMLINUX=y
- # CONFIG_USB_EPSON2888 is not set
- # CONFIG_USB_KC2190 is not set
- CONFIG_USB_NET_ZAURUS=y
- # CONFIG_USB_NET_CX82310_ETH is not set
- # CONFIG_USB_NET_KALMIA is not set
- # CONFIG_USB_NET_QMI_WWAN is not set
- # CONFIG_USB_NET_INT51X1 is not set
- # CONFIG_USB_SIERRA_NET is not set
- # CONFIG_USB_VL600 is not set
- # CONFIG_USB_NET_CH9200 is not set
- CONFIG_FB_SIMPLE=y
- # CONFIG_FRAMEBUFFER_CONSOLE is not set
- CONFIG_SND_SIMPLE_CARD_UTILS=y
- CONFIG_SND_SIMPLE_CARD=y
- CONFIG_USBIP_CORE=y
- # CONFIG_USBIP_VHCI_HCD is not set
- # CONFIG_USBIP_HOST is not set
- # CONFIG_USBIP_VUDC is not set
- # CONFIG_USBIP_DEBUG is not set
Rootfs
Start with petalinux-config -c rootfs
Changes:
- i2c-tools
- alsa-plugins
- alsa-lib-dev
- libasound
- alsa-conf-base
- alsa-conf
- alsa-utils
- alsa-utils-aplay
- busybox-httpd
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
rpicam
Application used to enable and configure Raspbery Pi camera module
See: \os\petalinux\project-spec\meta-user\recipes-apps\rpicam\files
fbgrab
Application used to take screenshot from camera
See: \os\petalinux\project-spec\meta-user\recipes-apps\fgrab
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
See: \os\petalinux\project-spec\meta-user\recipes-apps\webfwu\files
Kernel Modules
te-audio-codec
Simple module stab to use audio interface.
See: \os\petalinux\project-spec\meta-user\recipes-modules\te-audio-codec\files
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_dch |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | 2*,*,3*,4* |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Document Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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| Page info |
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infoType | Modified by |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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