Zynq PS Design with Linux Example and Camera Demo.
Refer to http://trenz.org/te0727-info for the current online version of this manual and other available documentation.
RPI Camera 1.3 or 2.1
Special FSBL for QSPI programming
Oleksandr Kiyenko/ John Hartfiel
Release Notes and Know Issues
To be fixed version
|Petalinux does not restart after first booting||use 0001-QSPI-s25fl127_8-2020_2.patch from|
|Error message during boot "memory reservation failed"||During boot message "ERROR: reserving fdt memory region failed (addr=1fc00000 size=400000)" occures.|
automatically camera selection failed
select camera manually on init.sh
needed, Vivado is included into Vitis installation
HardwareBasic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
|Module Model||Board Part Short Name||PCB Revision Support||DDR||QSPI Flash||EMMC||Others||Notes|
*used as reference
Design supports following carriers:
Additional HW Requirements:
Use USB2.0 or higher for power supply via USB
Connect to USB2 or better USB3 Hub for proper power supply over USB
Raspberry Pi Camera Rev 1.3 or Camera Rev 2.1
DELL Model Number: U2412M*
HDMI to Mini HDMI adapter
*used as reference
For general structure and usage of the reference design, see Project Delivery - Xilinx devices
|Vivado Project will be generated by TE Scripts|
|Vitis||<project folder>\sw_lib||Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation|
|PetaLinux||<project folder>\os\petalinux||PetaLinux template with current configuration|
|init.sh||<project folder>\misc\sd\||Additional Initialization Script for Linux (used to enable camera)|
|BIF-File||*.bif||File with description to generate Bin-File|
|BIN-File||*.bin||Flash Configuration File with Boot-Image (Zynq-FPGAs)|
|BIT-File||*.bit||FPGA (PL Part) Configuration File|
Distro Boot file
|DebugProbes-File||*.ltx||Definition File for Vivado/Vivado Labtools Debugging Interface|
|Diverse Reports||---||Report files in different formats|
|Hardware-Platform-Description-File||*.xsa||Exported Vivado hardware description file for Vitis and PetaLinux|
|LabTools Project-File||*.lpr||Vivado Labtools Project File|
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
|OS-Image||*.ub||Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)|
|Software-Application-File||*.elf||Software Application for Zynq or MicroBlaze Processor Systems|
Converted Software Application for MicroBlaze Processor Systems
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also be executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"prebuilt\os\petalinux\<ddr size>" or " \prebuilt\os\petalinux\<short name>"
Generate Programming Files with Vitis
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
Boot.bin on QSPI Flash and image.ub and boot.scr on SD.
- Connect USB Power In to get power on module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Remove cable from USB Power In
- Copy image.ub and boot.scr on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Important: Do not copy Boot.bin on SD (it is not used; see SD note), only other files.
- Copy init.sh on SD
- location: <project folder>/misc/sd/
- Insert SD-Card in SD-Slot.
- Connect USB Power In to get power on module
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot (fsbl, u-boot) and SD for secondary boot (image.ub, boot.src)
Not used on this Example.
Prepare HW like described in section Programming
Connect UART USB (most cases same as JTAG)
Insert SD Card with image.ub and boot.src
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr
Power On PCBboot process
1. Zynq Boot ROM loads FSBL from QSPI into OCM,
2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Open Serial Console (e.g. putty)
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Note: Wait until Linux boot finished
You can use Linux shell now.
Camera stream will be enabled via init.sh script on SD
Take image from camera (must be enabled with init.sh script):
System Design - Vivado
USB PHY RST
Basic module constraints
Design specific constraint
Software Design - Vitis
For Vitis project creation, follow instructions from:
ApplicationTemplate location: "<project folder>\sw_lib\sw_apps\"
TE modified 2020.2 FSBL
- Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device ID
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
TE modified 2020.2 FSBL
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
Hello TE0727 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Start with petalinux-config -c u-boot
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
Must be add manually, see template
Start with petalinux-config -c kernel
# CONFIG_FRAMEBUFFER_CONSOLE is not set
- Add 0001-QSPI-s25fl127_8-2020_2.patch to "<project folder>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\"
Start with petalinux-config -c rootfs
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Script App to load init.sh from SD Card if available.
Application used to enable and configure Raspbery Pi camera module
Application used to take screenshot from camera
No additional software is needed.
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