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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Overview
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MicroBlaze Design with Linux example.
Refer to http://trenz.org/te0713-info for the current online version of this manual and other available documentation.
For directly getting started with the prebuilt files jump to the section Launch.
Key Features
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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*used as reference |
Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx AMD devices
Design Sources
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Additional Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx AMD Development ToolsTools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For current script limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
- Configure the boot.scr file as needed, see Distro Boot with Boot.scr
Add Linux files (uboot.elf, image.ub, boot.scr) to prebuilt folder
Info - copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- (Optional) BlockRam Firmware Update
Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Regenerate Vivado Project or Update Bitfile only with new "spi_bootloader.elf" and "scu_te0713.elf"
Code Block language bash theme Midnight TE::hw_build_design -export_prebuilt TE::sw_run_vitis -all
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select Create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)
- Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.Code Block language py theme Midnight title run on Vivado TCL (Script programs u-boot.mcs on QSPI flash) TE::pr_program_flash -swapp u-boot
SD-Boot mode
Not used on this Example.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info Note: See TRM of the Carrier, which is used.
- Power On PCB and push the reset button if present on carrier.
Expand title boot process 1. FPGA Loads Bitfile from Flash,
2. SREC SPI Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
3. U-boot loads Linux from QSPI Flash into DDR
Scroll Title anchor Figure_VHM1 title Boot process takes a while, please wait... Image RemovedImage Added
Linux
- Open Serial Console (e.g. PuTTY)
- Speed: 9600
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight petalinux login: root Password: root
Info Note: Wait until Linux boot finished
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Monitoring:
- MIG Calibration Done
- Main Reset
- MicroBlaze Reset
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System Design - Vivado
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Block Design
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Constraints
Basic module constraints
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
Design specific constraints
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] # # # |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
srec_spi_bootloader
TE modified 2021.2 SRECSPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash (some reinitialisation)
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
hello_te0713
Hello TE0713 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate the file u-boot.srec(obsolete). Vivado is used to generate the file *.mcs
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
(Tipp: Search for Settings with shortcut "Shift"+"/")
Changes:
- Set flash content offset(Set kernel flash Address to 0x900000 and Kernel size to 0xA00000)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE =
0x5E00000x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE =
0x3000000x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000
0x20000(bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000 (kernel)
(with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xA00000)
U-Boot
Start with petalinux-config -c u-boot
Changes: (e.g. activate CONFIG via petalinux GUI like [*] Environment is not stored)
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
Content of platform-top.h located in <plnx-proj-root>/project-spec/meta-user/recipes-bsp/u-boot/files:
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#include <configs/microblaze-generic.h> #include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 |
Device Tree
Content of system-user.dtsi located in <petalinux project directory>/project-spec/meta-user\recipes-bsp\device-tree\file:
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/include/ "system-conf.dtsi" / { }; |
Kernel
Start with petalinux-config -c kernel
Changes:
- No changes.
Rootfs
Start with petalinux-config -c rootfs
Changes:
# CONFIG_dropbear is not set
# CONFIG_dropbear-dev is not set
# CONFIG_dropbear-dbg is not set
# CONFIG_package-group-core-ssh-dropbear is not set
# CONFIG_packagegroup-core-ssh-dropbear-dev is not set
# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
# CONFIG_imagefeature-ssh-server-dropbear is not set
Applications
No additional application.
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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