MicroBlaze Design with Linux example.
Refer to http://trenz.org/te0713-info for the current online version of this manual and other available documentation.
For directly getting started with the prebuilt files jump to the section Launch.
- Vitis/Vivado 2021.2
Release Notes and Know Issues
|Issues||Description||Workaround||To be fixed version|
|petalinux-build failed on 2020.2||---||activate "Networking support" in petalinux-config -c u-boot|
|Vitis||2021.2||needed, Vivado is included into Vitis installation|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
|Module Model||Board Part Short Name||PCB Revision Support||DDR||QSPI Flash||EMMC||Others||Notes|
*used as reference
Design supports following carriers:
*used as reference
Additional HW Requirements:
|USB Cable for JTAG/UART||Check Carrier Board and Programmer for correct typ|
|XMOD Programmer||Carrier Board dependent, only if carrier has no own FTDI|
For general structure and of the reference design, see Project Delivery - Xilinx devices
|Vivado Project will be generated by TE Scripts|
|Vitis||<project folder>/sw_lib||Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation|
|PetaLinux||<project folder>/os/petalinux||PetaLinux template with current configuration|
|BIT-File||*.bit||FPGA (PL Part) Configuration File|
|Boot Source||*.scr||Distro Boot file|
|DebugProbes-File||*.ltx||Definition File for Vivado/Vivado Labtools Debugging Interface|
|Diverse Reports||---||Report files in different formats|
|Hardware-Platform-Specification-Files||*.xsa||Exported Vivado Hardware Specification for Vitis and PetaLinux|
|LabTools Project-File||*.lpr||Vivado Labtools Project File|
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
|OS-Image||*.ub||Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)|
|Software-Application-File||*.elf||Software Application for Zynq or MicroBlaze Processor Systems|
Converted Software Application for MicroBlaze Processor Systems
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
- Xilinx Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For current script limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
build images are located in the "<plnx-proj-root>/images/linux" directory
- Configure the boot.scr file as needed, see Distro Boot with Boot.scr
Add Linux files (uboot.elf, image.ub, boot.scr) to prebuilt folder
- copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder " prebuilt\os\petalinux\<ddr size>" or " \prebuilt\os\petalinux\<short name>"
Generate Programming Files with Vitis
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- (Optional) BlockRam Firmware Update
Copy "\prebuilt\software\<short name>\spi_bootloader.elf" into " \firmware\microblaze_0\"
Regenerate Vivado Project or Update Bitfile only with new "spi_bootloader.elf"
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select Create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)
- Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.
Not used on this Example.
Not used on this Example.
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Note: See TRM of the Carrier, which is used.
- Power On PCB and push the reset button if present on carrier.boot process
1. FPGA Loads Bitfile from Flash,
2. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR,
3. U-boot loads Linux from QSPI Flash into DDRBoot process takes a while, please wait...
- Open Serial Console (e.g. PuTTY)
- Speed: 9600
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Note: Wait until Linux boot finished
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- MIG Calibration Done
- Main Reset
- MicroBlaze Reset
System Design - Vivado
Basic module constraints
Design specific constraints
Software Design - Vitis
For Vitis project creation, follow instructions from:
Template location: ./sw_lib/sw_apps/
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.
- Modified Files: bootloader.c
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
Hello TE0713 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate the file u-boot.srec(obsolete). Vivado is used to generate the file *.mcs
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
(Tipp: Search for Settings with shortcut "Shift"+"/")
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000 (kernel)
(with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xA00000)
Start with petalinux-config -c u-boot
Changes: (e.g. activate CONFIG via petalinux GUI like [*] Environment is not stored)
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
Content of platform-top.h located in <plnx-proj-root>/project-spec/meta-user/recipes-bsp/u-boot/files:
Content of system-user.dtsi located in <petalinux project directory>/project-spec/meta-user\recipes-bsp\device-tree\file:
Start with petalinux-config -c kernel
- No changes.
Start with petalinux-config -c rootfs
# CONFIG_dropbear is not set
# CONFIG_dropbear-dev is not set
# CONFIG_dropbear-dbg is not set
# CONFIG_package-group-core-ssh-dropbear is not set
# CONFIG_packagegroup-core-ssh-dropbear-dev is not set
# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
# CONFIG_imagefeature-ssh-server-dropbear is not set
No additional application.
No additional software is needed.
Appx. A: Change History and Legal Notices
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