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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware
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Template Revision 2.1

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

  • Change List 2.0 to 2.1
    • Fix problem with pdf export and side scroll bar
  • Change List 1.9.1 to 2.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator

Overview

Firmware for PCB CPLD with designator U26 : LCMX02-256HC

Feature Summary

  • Power Management
  • Reset
  • CPLD JTAG
  • Boot Mode
  • PUDC
  • ETH
  • LED
  • I2C

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
/ LEDout25NONE3.3VINRed LED D3
CONFIGout4NONE1.8VETH config pin
EN1 /

...

EN1in32UP3.3VINB2B Power Enable - Old name from PCB REV04 and earlier : EN1 / EN_SC3
JTAGEN / ---in26---3.3VINJTAG enable for CPLD Firmware update
MODE /MODE

...

in30UP3.3VINB2B Boot Mode Pin- Old name from PCB REV04 and earlier :  MODE /MODE_SC1
MODE0_R /

...

MODE0_

...

Rout12NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE0_R / BOOT_R0
MODE2_R /

...

MODE2_

...

Rout17NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE2_R / BOOT_R2
MODE3_R /

...

MODE3_

...

Rout13NONE3.3VZynq Boot Mode Pin- Old name from PCB REV04 and earlier : MODE3_R / BOOT_R3
MR /

...

MRout10UP3.3VZynq Reset

...

- Old name from PCB REV04 and earlier : MR / POR_B
SPI_SCK_FB/VCFG1out8NONE

...

3.3VOnly for PCB REV05 and later

...

RST / ------9---

...

3.3V/ currently_not_used
NOSEQ / NOSEQ

...

...

inout29UP3.3VIN

...

NOSEQ pin- Old name from PCB REV04 and earlier : NOSEQ / NOSEQ_SC4
PG_3V3 / PG_

...

3V3in28UP3.3VINPower Good- Old name from PCB REV04 and earlier :  PG_3V3 / PG_1V5
PG_

...

ALL / PG_

...

ALLin27UP3.3VIN

Power Good -  Old name from PCB REV04 and earlier:  PG_DDR_PWR / PG_1V8

PG_MGT / PG_MGTin11NONE3.3V/ currently_not_used
PGOOD /

...

PGOOD

...

inout1UP3.3VINB2B Power Good- Old name from PCB REV04 and earlier :  PGOOD / STAT_SC2
PHY_LED1in5UP1.8VPHY LED Pin
RESIN /

...

RESINin23UP3.3VINB2B Reset - Old name from PCB REV04 and earlier :  RESIN / nRST_SC0
SCL33 /

...

SCL33in14UP3.3V

...

I2C clock pin- Old name from PCB REV04 and earlier :  SCL33 / SCL
SDA33 /

...

SDA33inout16UP3.3V

...

I2C data pin- Old name from PCB REV04 and earlier :  SDA33 / SDA
X0 /

...

X0out21NONEVCCIO34FPGA Pin K8 - Old name from PCB REV04 and earlier : X0 / XA_SC
X1 /

...

X1out20NONEVCCIO34PUDC FPGA Pin K7- Old name from PCB REV04 and earlier : X1 / XB_SC


Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGENB pin of CPLD (pin 26) (logical one for CPLD, logical zero for FPGA). This pin is connected to B2B (JM1-pin 89) directly. On the carrier board can be this pin enabled or disabled with a dip switch.

CPLD JTAGEN (B2B JM1-89)Description
0FPGA access
1CPLD access

Power

PGOOD  is  PG_3V3 and PG_

...

ALL and EN1

There is no additional power control.

Reset

POR_B is RESIN and PG_3V3 and PG_

...

ALL and EN1 with some delay.

PUDC

X1

...

Boot Mode

  • MODE0_R is constant one.
  • MODE2_R is not MODE.
  • MODE3_R  is constant zero.

...

can be changed by changing the PUDC generic parameter in firmware source code. In released zip folder can be found all jed file according to PUDC state options.

Boot Mode

Boot mode can be set either by hardware (dip-switch) on the carrier board or by Linux console. Even after booting you can change the boot mode. After changing the boot mode FPGA is restarted automatically by CPLD. To change boot mode a state machine  continuously monitors the corresponding register that can be change via I2C interface between CPLD and FPGA. After changing this register according to desired boot mode , CPLD will reset FPGA.

Change MethodBoot ModeCPLD PGOOD Pin (B2B Pin JM1-30)CPLD MODE Pin (B2B Pin JM1-32)Description
HardwareJTAG00
Hardware---01
HardwareSD Card10
HardwareQSPI11


Change MethodBoot ModeCommand in Linux consoleCommand in FSBLDescription
SoftwareJTAG
i2cset -y 0 0x20 0x1 0x91
iic_write8(0x20,0x1,0x91)
0x20 is device address. 0x1 is register address.
SoftwareSD Card
i2cset -y 0 0x20 0x1 0x93
iic_write8(0x20,0x1,0x93)
0x20 is device address. 0x1 is register address.
SoftwareQSPI
i2cset -y 0 0x20 0x1 0x92
iic_write8(0x20,0x1,0x92)
0x20 is device address. 0x1 is register address.

ETH

CONFIG is constant zero.

PHY_LED1 is connected to X0.

LED

LED

...

stateDescription
ONBoot mode is changed by software either in linux console or by FSBL code.
OFFBoot mode is selected only by hardware. ( Dip switch on the carrier board)

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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    • Metadata is only used of compatibility of older exports

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Page info

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infoTypeModified

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date
dateFormatyyyy-MM-dd
typeFlat

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infoTypeCurrent

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version
prefixv.
type

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REV03REV05,REV04,REV03

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infoTypeModified by
typeFlat

  • working in process

2018-07-17

v.6REV02REV04,REV03John Hartfiel

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  • REV02 , Firmware released  2015-08-18
2018-07-16

v.1



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IN:Legal Notices
IN:Legal Notices



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