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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
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Overview
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Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Note: Design contains also Board Part Files for TE0807 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
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Additional HW Requirements:
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For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices
Design Sources
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Additional Sources
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
- Xilinx AMD Development ToolsTools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which ends with *_tebf0808
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis
- Copy PetaLinux build image files to prebuilt folder
- copy u-boot.elf,
- system.dtb, bl31.elf, image.ub and boot.scr from"<plnx-proj-root>/images/linux" to prebuilt folder
- system.dtb, bl31.elf, image.ub and boot.scr from"<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::
Generate Programming Files with Vitis
Code Block TE::language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Copy PetaLinux build image files to prebuilt folder
Launch
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0807
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area
SD-Boot mode
- Copy image.ub, boot.scr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr- (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional with TEBF0808) Connect SATA Disc
- (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional with TEBF0808) Connect Network Cable
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2Expand title boot process 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
FSBL loads ATF(bl31.
elf) and U-boot from SD/QSPI into DDR, 3.
U-boot load Linux from SD.
.into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password default disabled with 2021.2 petalinux release petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)
Option Features
- Webserver to get access to ZynqMP
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to ZynqMP
Vivado Hardware Manager
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RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Set Enable to send Write date over RGPIO interface.
- Control:
- LEDs: XMOD 2(without green dot) and HD LED are accessible.
- CAN_S
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PS Interfaces
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Activated interfaces:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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#System Controller IP #J3:31 LED_HD set_property PACKAGE_PIN K11 [get_ports BASE_sc0] #J3:41 set_property PACKAGE_PIN E14 [get_ports BASE_sc5] #J3:45 set_property PACKAGE_PIN C12 [get_ports BASE_sc6] #J3:47 set_property PACKAGE_PIN D12 [get_ports BASE_sc7] #J3:32 set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io] #J3:34 set_property PACKAGE_PIN K13 [get_ports BASE_sc11] #J3:36 set_property PACKAGE_PIN A13 [get_ports BASE_sc12] #J3:38 set_property PACKAGE_PIN A14 [get_ports BASE_sc13] #J3:40 set_property PACKAGE_PIN E12 [get_ports BASE_sc14] #J3:42 set_property PACKAGE_PIN F12 [get_ports BASE_sc15] #J3:46 CAN S set_property PACKAGE_PIN A12 [get_ports BASE_sc16] #J3:48 LED_XMOD set_property PACKAGE_PIN B12 [get_ports BASE_sc17] #J3:50 CAN TX set_property PACKAGE_PIN B14 [get_ports BASE_sc18] #J3:52 CAN RX set_property PACKAGE_PIN C14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # PLL #J4:74 #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ] set_property PACKAGE_PIN H14 [get_ports I2S_bclk ] set_property PACKAGE_PIN C13 [get_ports I2S_sdin ] set_property PACKAGE_PIN D14 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ] |
Software Design - Vitis
scroll-pdf | true |
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scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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For Vitis project creation, follow instructions from:
Application
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----------------------------------------------------------
FPGA Example
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2021.2 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11
TE modified 2021.2 xilisf_v5_11
- Changed default Flash type to 5.
----------------------------------------------------------
Zynq Example:
fsbl
TE modified 2021.2 FSBL
General:
- Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
fsbl_flash
TE modified 2021.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example:
----------------------------------------------------------
zynqmp_fsbl
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
----------------------------------------------------------
General Example:
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
# MGTs
# R8 MGT_224_CLK0_P -> B2B,J3-62 -> TEBF0808-04a_FMC_J5E-D5
# R7 MGT_224_CLK0_N -> B2B,J3-60 -> TEBF0808-04a_FMC_J5E-D4
# N8 MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
# N7 MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4
# L8 MGT_225_CLK0_P -> B2B,J3-67 -> TEBF0808-04a_FMC_J5E-B21
# L7 MGT_225_CLK0_N -> B2B,J3-65 -> TEBF0808-04a_FMC_J5E-B20
# J8 MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
# J7 MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3
# H10 MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
# H9 MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
# F10 MGT_226_CLK1_P -> B2B,J3-61 -> TEBF0808-04a_B230_CLK_P/CLK7_P -> B2B,J2-13 -> U5,51 -> Si5345 -> out7
# F9 MGT_226_CLK1_N -> B2B,J3-59 -> TEBF0808-04a_B230_CLK_N/CLK7_N -> B2B,J2-15 -> U5,50 -> Si5345 -> out7
# D10 MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
# D9 MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
# B10 MGT_227_CLK1_P -> B2B,J2-22 -> floating
# B9 MGT_227_CLK1_N -> B2B,J2-24 -> floating
set_property PACKAGE_PIN R8 [get_ports {MGT_CLK_IN_clk_p[0]}]
set_property PACKAGE_PIN N8 [get_ports {MGT_CLK_IN_clk_p[1]}]
set_property PACKAGE_PIN L8 [get_ports {MGT_CLK_IN_clk_p[2]}]
set_property PACKAGE_PIN J8 [get_ports {MGT_CLK_IN_clk_p[3]}]
set_property PACKAGE_PIN H10 [get_ports {MGT_CLK_IN_clk_p[4]}]
set_property PACKAGE_PIN F10 [get_ports {MGT_CLK_IN_clk_p[5]}]
set_property PACKAGE_PIN D10 [get_ports {MGT_CLK_IN_clk_p[6]}]
set_property PACKAGE_PIN B10 [get_ports {MGT_CLK_IN_clk_p[7]}]
# MGTs
# R8 MGT_224_CLK0_P -> B2B,J3-B27 -> TEBF0818-01_FMC_J5E-D5
# R7 MGT_224_CLK0_N -> B2B,J3-B26 -> TEBF0818-01_FMC_J5E-D4
# N8 MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
# N7 MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4
# L8 MGT_225_CLK0_P -> B2B,J3-C26 -> TEBF0818-01_FMC_J5E-B21
# L7 MGT_225_CLK0_N -> B2B,J3-C25 -> TEBF0818-01_FMC_J5E-B20
# J8 MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
# J7 MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3
# H10 MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
# H9 MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
# F10 MGT_226_CLK1_P -> B2B,J3-D27 -> TEBF0818-01_CLK7_P -> B2B,J2-D5 -> U5,51 -> Si5345 -> out7
# F9 MGT_226_CLK1_N -> B2B,J3-D26 -> TEBF0818-01_CLK7_N -> B2B,J2-D6 -> U5,50 -> Si5345 -> out7
# D10 MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
# D9 MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
# B10 MGT_227_CLK1_P -> B2B,J2-A6 -> floating
# B9 MGT_227_CLK1_N -> B2B,J2-A7 -> floating |
Software Design - Vitis
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zynqmp_fsbl
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_fsbl_flash
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For Vitis project creation, follow instructions from:
PetaLinux KICKstartApplication
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- generate u-boot.dtb:
- CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_ENV_OVERWRITE=y
- CONFIG_SYS_I2C_EEPROM_ADDR=0x50
- CONFIG_SYS_I2C_EEPROM_BUS=7
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- # CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
Change platform-top.h:
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Device Tree
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---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: -------------------- | ||||
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/include/ "system-conf.dtsi"
/ {
chosen {
xlnx,eeprom = &eeprom;
};
};
/* ------------------ gtr-------------------- */ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; refclk1:psgtr_sata_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000>; }; //refclk0:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; }; &psgtr { clocks = <&refclk1 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref1\0ref2\0ref3"; }; /*fsblTE modified 2022.2 FSBL General:
Module Specific:
------------------------------------- SD-------------------- */ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /*- ZynqMP Example: -------------------------------------- USB-------------------- */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*zynqmp_fsblTE modified 2022.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ------------------------------------- ETH PHY-------------------- */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*- General Example: ------------------------------ QSPI-------------------- */ &qspi { #address- cells = <1>; #size- cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi- nor"; reg = <0x0>; #address- cells = <1>; #size- cells = <1>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP1 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 {// SFP2 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // TEBF0808 EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; i2c@6 { // TEBF0808 FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0808 Firefly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // TEBF0808 Firefly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { //TEBF0808 CPLD #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { //TEBF0808 Firefly PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 PMOD P3 #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; | ||||
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--- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 2022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0807_TEBF0808"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_ZYNQ_MAC_IN_EEPROM is not set
- CONFIG_NET_RANDOM_ETHADDR is not set
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
- Identification
- CONFIG_IDENT_STRING=" TE0807_TEBF0808"
Change platform-top.h:
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/include/ "system-conf.dtsi" /include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; refclk1:psgtr_sata_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000>; }; //refclk0:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; }; &psgtr { clocks = <&refclk1 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref1\0ref2\0ref3"; }; /*------------------ SDgtr --------------------*/ &sdhci0 { */ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; // disable-wp; #clock-cells = <0x00>; no-1-8-vclock-frequency = <27000000>; }; &sdhci1 refclk2:psgtr_pcie_usb_clock { compatible //= disable"fixed-wpclock"; no-1-8-v; }; /*------------------ USB --------------------*/ &dwc3_0 #clock-cells = <0x00>; clock-frequency = <100000000>; }; refclk1:psgtr_sata_clock { status compatible = "okayfixed-clock"; dr_mode #clock-cells = "host"<0x00>; snps,usb3_lpm_capable; clock-frequency snps,dis_u3_susphy_quirk= <150000000>; }; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; //refclk0:psgtr_unused_clock { // maximum-speedcompatible = "superfixed-speedclock"; }; /*------------------ ETH PHY ----------------*/ &gem3 { // phy#clock-handlecells = <&phy0><0x00>; // phy0: phy0@1 { clock-frequency = <100000000>; device_type = "ethernet-phy"//}; }; &psgtr { clocks = <&refclk1 &refclk2 &refclk3>; /* ref clk instances used per reg = <1>;lane */ clock-names }= "ref1\0ref2\0ref3"; }; /*------------------ QSPISD --------------------*/ &qspisdhci0 { // #address-cells = <1>disable-wp; #size-cells = <0>; status = "okay"; flash0: flash@0 no-1-8-v; }; &sdhci1 { compatible = "jedec,spi-nor"// disable-wp; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; };no-1-8-v; }; /*------------------- I2CUSB --------------------*/ &i2c0dwc3_0 { i2cswitch@73 { // u compatiblestatus = "nxp,pca9548okay"; #address-cells = <1>dr_mode = "host"; #size-cells = <0>snps,usb3_lpm_capable; reg = <0x73>snps,dis_u3_susphy_quirk; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembledsnps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; #addressmaximum-cellsspeed = <1>; "super-speed"; }; /*------------------ ETH PHY --------------------*/ &gem3 { /delete-property/ local-mac-address; #sizephy-cellshandle = <0><&phy0>; nvmem-cells = <ð0_addr>; regnvmem-cell-names = <0>"mac-address"; }; phy0: phy0@1 { i2c@1 { // SFP TEBF0808 PCF8574DWRdevice_type = "ethernet-phy"; #address-cellsreg = <1>; }; }; /*----------------- SATA PHY #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP1 TEBF0808 --------------------*/ &sata { ceva,p0-burst-params = <0x13084a06>; ceva,p0-cominit-params = <0x18401828>; ceva,p0-comwake-params = <0x614080e>; ceva,p0-retry-params = <0x96a43ffc>; ceva,p1-burst-params = <0x13084a06>; ceva,p1-cominit-params = <0x18401828>; ceva,p1-comwake-params = <0x614080e>; ceva,p1-retry-params = <0x96a43ffc>; }; /*-------------------- QSPI ---------------------*/ &qspi { #address-cells = <1>; #size-cells = <0>; reg = <3>status = "okay"; flash0: flash@0 };{ i2c@4compatible {// SFP2 TEBF0808= "jedec,spi-nor"; reg #address-cells = <1><0x0>; #size#address-cells = <0><1>; reg#size-cells = <4><1>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2c@5i2cswitch@73 { // u TEBF0808 EEPROM compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; reg = <5> i2c-mux-idle-disconnect; i2c@0 { // MCLK eeprom:TEBF0808 eeprom@50 {SI5338A, 570FBB000290DG_unassembled reg = <0>; compatible = "atmel,24c08"; }; i2c@1 { // SFP reg = <0x50>;TEBF0808 PCF8574DWR reg = }<1>; }; i2c@6i2c@2 { // TEBF0808 FMC PCIe #address-cellsreg = <1><2>; }; #size-cells = <0>; i2c@3 { // SFP1 TEBF0808 reg = <6><3>; }; i2c@7i2c@4 { // SFP2 TEBF0808 USB HUB #address-cellsreg = <1><4>; }; #size-cells = <0>; i2c@5 { // TEBF0808 EEPROM reg = <7>; reg = }<5>; }; i2cswitch@77 { // u eeprom: eeprom@50 { compatible = "nxp,pca9548"; #address-cellscompatible = <1> "microchip,24aa025", "atmel,24c02"; #size-cells = <0>; reg = <0x77><0x50>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0><1>; reg = <0>; eth0_addr: eth-mac-addr@FA { }; i2c@1 { //reg i2c= Audio<0xFA Codec0x06>; #address-cells = <1>}; #size-cells = <0>}; reg = <1>}; i2c@6 { // TEBF0808 /*FMC adau1761:reg adau1761@38= {<6>; }; compatiblei2c@7 = "adi,adau1761"; { // TEBF0808 USB HUB reg = <0x38><7>; }; }; i2cswitch@77 { // u */ compatible }= "nxp,pca9548"; i2c@2reg { // TEBF0808 Firefly A= <0x77>; #address-cells = <1>i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 #size-cells = <0>;PMOD P1 reg = <2><0>; }; i2c@3i2c@1 { // TEBF0808i2c FireflyAudio BCodec #address-cellsreg = <1>; #size-cells = <0>;/* regadau1761: =adau1761@38 <3>;{ }; i2c@4compatible { //Module PLL Si5338 or SI5345 = "adi,adau1761"; #address-cellsreg = <1><0x38>; #size-cells = <0>}; reg = <4>;*/ }; i2c@5i2c@2 { // TEBF0808 Firefly CPLDA #address-cellsreg = <1><2>; }; #size-cells = <0>; i2c@3 { // TEBF0808 Firefly B reg = <5><3>; }; i2c@6i2c@4 { //TEBF0808 Firefly PCF8574DWRModule PLL Si5338 or SI5345 #address-cellsreg = <1><4>; }; i2c@5 #size-cells = <0>;{ //TEBF0808 CPLD reg = <6><5>; }; i2c@7i2c@6 { // TEBF0808 PMODFirefly P3PCF8574DWR #address-cellsreg = <1><6>; }; #size-cells = <0>; i2c@7 { // TEBF0808 PMOD P3 reg = <7>; }; }; }; |
FSBL patch
Must be add manually, see template
Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
- # CONFIG_CPU_IDLE is not set
- # CONFIG_CPU_FREQ is not set
- CONFIG_EDAC_CORTEX_ARM64=y
- Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_HWMON is not set
- # CONFIG_NVME_TCP is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_auto-login
- CONFIG_NVM=y
- CONFIG_NVM_PBLK=y
- CONFIG_NVMADD_PBLKEXTRA_DEBUG=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_busybox-httpd=y
- USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
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te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for ZynqMP access. Need busybox-httpd
Additional Software
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SI5345
File location "<project folder>/\misc/\PLL/\Si5345_B/\Si5345-*.slabtimeproj"
General documentation how you work with these project will be available on Si5345
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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