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Custom_table_size_100

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  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

DateVersionChangesAuthor

4.2
  • Changes Xilinx to AMD
ED

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Perihery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

The Trenz Electronic TE0950-02 is a powerful adaptive SoC evaluation board, equipped with an AMD Versal™ AI Edge VE2302 device. Furthermore, the board is equipped with up to 8GB DDR4 SDRAM, 128 MByte SPI Flash and an  eMMC for configuration and data storage as well as powerful switching power supplies for all required voltages. Inputs and outputs are provided by robust, flexible and cost-effective high-speed connectors.

Refer to http://trenz.org/te0950-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • SoC
    • AMD Versal™ AI Edge XCVE2302-1LSESFVA784 device (engineering sample) 1)
      • Package: A784
      • Device:  VE2002, VE2102, VE2202, VE2302, VM1102 1)
      • Speed: -1, -2, -3 1)
      • Temperature: I, E 1)
  • RAM/Storage
    • DDR4 SDRAM*
      • Data width: 64bit
      • Size: def. 4GB, up to 8 GByte possible 1)
      • Speed: up to 3200Mb/s 2)
    • 128 MByte SPI Flash (primary boot option)
      • Data width: 8bit
      • size: def. 128MB, up to 512MB possible 1)
    • MicroSD card (primary boot option)
    • e.MMC (secondary boot option) 1)
      • Data width: 8bit
      • size: def. 32GB 1)
    • EEPROM with MAC-address
  • On Board
    • AMD Artix™ 7 FPGA as configurable Levelshifter/MUX for FMC and other 3.3 V IOs
      • 32 MByte SPI Flash
      • 1 dip switch
      • 2 LEDs
    • USB 2.0 Host/Device/OTG (type Micro A/B connector)
    • USB JTAG + UART Micro-USB B
    • Gigabit Ethernet RJ45
    • Output
      • 2 LEDs (1 x MIO, 1 x PL)
    • Input
      • 1 push button
      • 3 dip switches (2 x MIO, 1 x PL)
      • Reset button
  • Interface
    • zQSFP
      • 4 GTYP Transceiver
    • 2 x CRUVI HS
      • each optimized for 4 Lane MIPI, one with reduced pinout
    • 2 x CRUVI LS
    • CSI-2 connector
      • optimized for camera, 2 lane MIPI
    • FMC
      • 4 GTYP Transceiver
      • 34 LA diff pairs to Levelshifter/MUX
  • Power
    • 12 V plug
  • Dimension
    • 150 mm x 120 mm
  • Notes
    • 1) depends on assembly version
    • 2) depends on used DDR4

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
title-alignmentcenter
titleTE0950 block diagram

Scroll Ignore

draw.io Diagram
bordertrue
diagramNameFigure_OV_BD
simpleViewerfalse
width
linksauto
tbstyletop
lboxtrue
diagramWidth680
revision1


Scroll Only


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_MC
title-alignmentcenter
titleTE0950 main components


Scroll Ignore

draw.io Diagram
borderfalse
diagramNameFigure_OV_MC
simpleViewerfalse
width
linksauto
tbstyletop
diagramDisplayName
lboxtrue
diagramWidth906
revision4


Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


  1. SoC (Versal) U1
  2. DDR4 U8, U9, U10, U11
  3. eMMC U25
  4. dual QSPI Configuration Flash (Versal) U23, U24
  5. ETH Phy U32
  6. MAC EEPROM U35
  7. USB 2.0 Phy U27
  8. Jumper (USB Device/Host/OTG) J5
  9. Artix FPGA (Levelshifter/MUX for FMC IOs) U13
  10. OSPI Configuration Flash (Artix) U14
  11. FTDI JTAG/UART to USB Bridge U15
  12. FTDI Configuration EEPROM U17
  13. zQSFP U12/J1
  14. LPC FM J3
  15. CRUVI HS J10, J11
  16. CRUVI LS J12, J13
  17. CSI CAM Connector J15
  18. SD-CARD Slot J4
  19. RJ45 ETH jack J9
  20. micro USB A/B Connector J8
  21. micro USB B Connector (JTAG/UART) J2
  22. 4 Pin FAN Connector J17
  23. Power Input Jack
  24. Reset Push Button S3
  25. User Push Button S1
  26. Dip Switches (JTAG Selection, User) S4
  27. Dip Switches (Bootmode, User) S2
  28. Dip Switches (FMC VADJ Selection, User) S5
  29. LEDs (Power) D8, D9, D10
  30. LEDs (Status/User) D0, D1, D2, D3 D4, D6, D11

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Scroll Title
anchorTable_OV_IDS
title-alignmentcenter
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

DDR4 SDRAMnot programmed


eMMCnot programmed


dual Quad SPI Flash (Versal)

not programmed


MAC EEPROMnot programmed besides factory programmed MAC address


FTDI EEPROMFTDI configuration for JTAG/UART with AMD Vivado compatible license
Quad SPI Flash (Artix)Template Design with basic functionality (TBD)Design has to be adapted to use case.


Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
  • Table with all connectors and Designtor
  • List of different interfaces per connector
  • IO CNT (for FPGA IOs where functionality can be changed by customer)


Connectors

Scroll Title
anchorTable_SIP_C
title-alignmentcenter
titleBoard Connectors

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orientationportrait
sortDirectionASC
repeatTableHeadersdefault
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cellHighlightingtrue

Connector TypeDesignatorInterfaceIO CNTNotes
B2B J3LPC FMC

4x MGT Transeiver
34 DIFF / 68 SE


FMC LA pins from/to Artix. Artix FPGA has to be configured for use case.

B2BJ11CRUVI HS

12 DIFF / 24 SE
4 SE
8 SE

Full pinout, MIPI 4 Lanes optimized (XPIO)
(XPIO)
connected to Artix @3.3V
B2BJ10CRUVI HS

9 DIFF / 18 SE
2 SE
8 SE

Reduced pinout, MIPI 4 Lanes optimized (XPIO)

(XPIO)
connected to Artix @3.3V

B2BJ12CRUVI LS8 SEHD bank 302 @3.3V
B2BJ13CRUVI LS8 SEHD bank 302 @3.3V
CONJ1, U12zQSFP4x MGT Transeiver
CONJ15CSI-2 CAM3 DIFF / 6 SE
4 SE
MIPI 2Lanes (XPIO),
(I2C and GPIO) to HD Bank 302 @3.3V
CONJ9GB ETH4 DIFFLPD
CONJ8micro USB2.0 A/B1 DIFFHost/Device/OTG check J5 for HW configuration
CONJ2micro USB2.0 B1 DIFFJTAG/UART via FTDI
CONJ4micro SD 2.01 DIFFprimary boot option, routed via levelshifter U26
CONJ174 pin FAN2 SEFor SoC FAN with Tacho and PWM signals connected to Artix.



Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test PointSignalNotes1)
TP1PWR_PL_OK

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.


Scroll Title
anchorTable_SIP_TPs
title-alignmentcenter
titleTest Points Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
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sortEnabledfalse
cellHighlightingtrue

Test PointSignalNotes1)

TP32

GNDGND

TP29

12V12V
TP175V05V
TP163V33.3V
TP43, TP44GTYP_AVCC0.92V
TP46, TP47GTYP_AVTT1.2V
TP45GTYP_AVCC_AUX1.5V
TP48A_3V33.3V
TP191V01.0V
TP423V3_FMC3.3V
TP40FMC_VADJ

1.2V, S5A-C: OFF,OFF, OFF
1.8V, S5A-C: ON,OFF, OFF
2.5V, S5A-C: ON,ON, OFF
3.3V, S5A-C: ON,ON, ON

TP181V81.8V
TP39V_VCCAUX1.5V
TP41C_VADJ1.2V
TP35DDR_1V21.2V
TP33DDR_2V52.5V
TP36DDR_VTT0.6V

TP37

VREFA0.6V
TP38V_VCC_SOC0.8V May depend on assembly versions
TP34V_VCC_CORE0.7V May depend on assembly versions
TP1V_VCC_BATTInput for VCC_BAT supply when R21 removed. Default (R21 assembled) GND.
TP2V_FUSEInput for V_FUSE supply when R43 removed. Default (R43 assembled) GND.
TP3DDR4-TEN_0pulled-down to GND
TP4DDR4-TEN1pulled-down to GND
TP5DDR4-TEN2pulled-down to GND
TP6DDR4-TEN3pulled-down to GND
TP20PHY_LED2Function dependent on ETH PHY (U31) configuration.
TP21I2C_PMC_SCL@1.8V
TP23I2C_PMC_SDA@1.8V
TP22DCDC_5V0_SCL@3.3V Levelshifted I2C_PMC_SCL signal
TP24DCDC_5V0_SDA@3.3V Levelshifted I2C_PMC_SDA signal
TP25I2C1_SCL@1.8V
TP26I2C1_SDA@1.8V
TP27I2C_SYSMON_SCL@1.8V
TP28I2C_SYSMON_SDA@1.8V
TP7TCKJTAG TCK (Versal and Artix)
TP12TMSJTAG TCK (Versal and Artix)
TP10V_TDOJTAG TDO
TP8FTDI_TDI
TP9A_TDIJTAG TDI Artix, connected to FTDI_TDI  via DIP S4A
TP11V_TDIJTAG TDI Versal, connected to FTDI_TDI  via DIP S4B
TP13A_TDOJTAG TDO Versal, connected to VTDI  via DIP S4C
TP14F_UART_TX@3.3V, from Versal, levelshifted UART1_TX signal, to FTDI
TP15F_UART_RX@3.3V, from FTDI, levelshifted UART1_RX signal to Versal
TP31-Sense input of reset chip U38, connected to PG_GTYP_AVTT @3.3V via R203
TP30FAULTn_12V@12V, Fault signal of input protection U37

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotes
ETH PHYU10
  • B2B connector J1
  • SoC MIO
Gigabit ETH PHY



Scroll Title
anchorTable_OBP
title-alignmentcenter
titleOn board peripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorConnected ToNotes
Versal SoC: XCVE2302-1LSESFVA784-ES9780U1

-

Engineering Sample

DDR4: K48G165WC-BITDTCVU8, U9, U10, U11Versal XPIO


dual parallel QSPI: MT25QU512ABB8E12U23, U24Versal PMC/MIO

primary boot option

GB ETH PHY: 88E1512-A0-NNP2I000U31Versal MIO
USB PHY: USB3320-EZKU27Versal MIOUSB2.0
CLK 2x 200MhzU4, U5Versal XPIODDR4 controller, User
CLK 2x (156.25MHz, 125MHz)U6, U7Versal GTYP REFCLKFor QSFP MGTs.
eMMCU25Versal PMC/MIO

secondary boot option

eeprom 24AA025E48TU34
for MAC. I2C PS, Address 50H
User Dip 3xS2C, S2D
S4D

Versal MIO
Versal HD


User LED 2x D0
D1

Versal MIO
Versal HD

both green
Push ButtonS1Versal HD
Artix: XC7A35T-2CSG324CU13
  • Versal XPIO
    (14 DIFF / 28 SE)
  • FMC LA pins
Configurable levelshifter for FMC and other 3.3V periphery configuration signals
QSPI Artix: S25FL256SAGBH20U14Artix32MB
User LED 2xD2, D3ArtixD2 green, D3 red
User DipS5DArtix



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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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  • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
  • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)


Scroll Title
anchorTable_OV_CNTRL
title-alignmentcenter
titleController signal.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Connector+Pin

Signal Name

Direction1)Description




1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

  • Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details


Power Rails

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List of all Powerrails which are accessible by the customer

  • Main Power Rails and Variable Bank Power



Scroll Title
anchorTable_PWR_PR
title-alignmentcenter
titleModule power rails.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue


Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
















1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.


Scroll Title
anchorTable_BB_DH
title-alignmentcenter
titleBaseboard Design Hints

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue


SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes

















































Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

  • Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings *)

Scroll Title
anchorTable_TS_AMR
title-alignmentcenter
titleAbsolute maximum ratings

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Power Rail Name/ Schematic NameDescriptionMinMaxUnit




V




V




V




V




V




V




V




V




°C


*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
  • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


Scroll Title
anchorTable_TS_ROC
title-alignmentcenter
titleRecommended operating conditions.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



VSee  ???? datasheet.



°CSee  ???? datasheet.



Physical Dimensions

  • Module size: ?? mm × ?? mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ? mm.

PCB thickness: ?? mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_TS_PD
title-alignmentcenter
titlePhysical Dimension


Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Scroll Title
anchorTable_VCP_SO
title-alignmentcenter
titleTrenz Electronic Shop Overview

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Trenz shop TEXXXX overview page
English pageGerman page


Revision History

Hardware Revision History

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Set correct links to download  Carrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD
  • Example: 

    DateRevisionChangesDocumentation Link
    2020-11-25REV02
    • Resistors R14 and R15 was replaced by 953R (was 5K1)
    • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
    REV02



Scroll Title
anchorFigure_RV_HRN
title-alignmentcenter
titleBoard hardware revision number.


Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.


Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



Scroll Title
anchorTable_RH_HRH
title-alignmentcenter
titleHardware Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionChangesDocumentation Link





Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_RH_DCH
title-alignmentcenter
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • <add TRM change list here>

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices



Scroll Only


HTML
<style>
.wiki-content .columnLayout .cell.aside {
width: 0%;
}</style>



Scroll pdf ignore


Custom_fix_page_content

Table of contents

Table of Contents
outlinetrue