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| ETH1 | ETH2 | Pullup | Notes | |
|---|---|---|---|---|
| CTREF | J3.57 | J3.25 | Magnetics center tap voltage | |
| TD+ | J3.58 | J3.28 | on-board | |
| TD- | J3.56 | J3.26 | on-board | |
| RD+ | J3.52 | J3.22 | on-board | |
| RD- | J3.50 | J3.20 | on-board | |
| LED1 | J3.55 | J3.23 | on-board | |
| LED2 | J3.53 | J3.21 | on-board | |
| LED3 | J3.51 | J3.19 | on-board | |
| POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. |
| RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). |
It is recommended to add IOB TRUE constraint for the MII Interface pins.
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