Page History

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1. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
2. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
3. Red LED (DONE), D1
4. 256Mx16 DDR4-2400 SDRAM, U12
5. 256Mx16 DDR4-2400 SDRAM, U9
6. 256Mx16 DDR4-2400 SDRAM, U2
7. 256Mx16 DDR4-2400 SDRAM, U3
8. 12A PowerSoC DC-DC converter, U4
9. Quartz crystal, Y1
10. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
11. 10-channel programmable PLL clock generator, U5
12. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
13. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Quartz crystal, Y2
17. 256 Mbit serial NOR Flash memory, U7
18. 256 Mbit serial NOR Flash memory, U17

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

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The boot device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins accessible on B2B connector J2:

Table 2: Boot mode pins on B2B connector J2.

Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins PS_MODE0 ... PS_MODE3 (little-endian alignment):

Table 3: Selectable boot modes by dedicated boot mode pins.

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Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 SoM.

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The Xilinx Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 4: MGT lanes

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Table 5: MGT reference clock sources

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JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

Table 4: B2B connector pin-out of JTAG interface.

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For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 5: B2B connector pin-out of MPSoC's PS configuration bank.

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The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

Table 6: B2B connector pin-out of analog input pins

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Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

Table 8: TE0807-01 PS MIO mapping

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The TE0808 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

Table 10: Peripherals connected to the PS MIO pins.

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Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

Table 11: Programmable PLL clock generator input/output.

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The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

Table 12: B2B connector pin-out of Si5345A programmable clock generator.

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The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

Table 14: LED's description.

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 15: Maximum current of power supplies. *to be determined soon with reference design setup.

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The on-board voltages of the TE0808 TE0807 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

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The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

Table 16: Recommended operation conditions of DC-DC converter control signals.

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Power Rails

Table 16: TE0807-01 power rails

Bank Voltages

Table 17: TE0807-01 I/O bank voltages

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Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 18: Module absolute maximum ratings

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Recommended Operating Conditions

Table 19: Recommended operating conditions

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Hardware Revision History

Table 20: Hardware revision history table

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Table 21: Document change history

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