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Refer to https://wiki.trenz-electronic.de/display/PD/<name> for the current online version of this manual and other available documentation.

The Trenz Electronic TE0xxx-xx ... TE0724 is an industrial-grade ... module ... SoC module based on Xilinx Zynq-7010. It provides a gigabit ethernet transceiver, 1GByte of DDR3L SDRAM, 32 MByte Flash memory as configration and data storage. it includes strong pwerregulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

Key Features

List key features here, like FPGA type, amount and type of RAM, type of flash, etc.

• Xilinx Zynq XC7Z010-1CLG400I or XC7Z020-1CLG400I
• Dual-core ARM Cortex-A9 MPCore
• Max. 667 MHz
• Shock proof an vibration resistant
• Size 6 x 4 cm
• Plug-On-Modul with 1 × 160 Pin High-Speed connector
• 1 GByte DDR3L SDRAM
• 32 MByte QSPI Flash Speicher
• 1 x GBit Ethernet PHY
• 1 x MAC-Address EEPROM
• 128 KBit EEPROM
• 1 x CAN Transceiver
• On-Board DC/DC-regulators
• Excellent signal integrity due to well dirstributed supply pins

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Figure 1: TE0xxx-xx block diagram.

Main Components

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Add description list of PCB labels here...

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

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By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

Table 2: Selecting power-on boot device.

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I/O signals connected to the SoCs I/O bank and B2B connector: 

Table x: General overview of PL I/O signals connected to the B2B connectors.

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

Table x: MGT reference clock sources.

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JTAG access to the ... is provided through B2B connector .... 

Table 5: JTAG interface signals.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table x: System Controller CPLD I/O pins.

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Note that table column says "Signal Name", it should match the name used on the schematic.

Table x: Quad SPI interface signals and connections.

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Describe SD Card interface  shortly here if the module has one...

Table x: SD Card interface signals and connections.

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On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

Table x: ...

USB Interface

USB PHY is provided with ...

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

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On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

Table x: I²C slave device addresses.

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table : Programmable quad PLL clock generator inputs and outputs.

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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table : Reference clock signals.

On-board LEDs

Table : On-board LEDs.

Power and Power-On Sequence

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table : Typical power consumption.

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NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Table : Module power rails.

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Bank Voltages

Table : Module PL I/O bank voltages.

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Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

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Recommended Operating Conditions

Table : Module recommended operating conditions.

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Hardware Revision History

Table : Module hardware revision history.

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v.58

Table : Document change history.

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