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Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
QSPI Flash | Empty |
Signals, Interfaces and Pins
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JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through testpoints TP1-T4.
JTAG Signal | Testpoint |
|---|---|
| TCK | TP3 |
| TDI | TP1 |
| TDO | TP2 |
| TMS | TP4 |
LEDs
| LED | Color | Connected To | Description and Notes |
|---|---|---|---|
| D2 | Red | MIO9, U1 | |
| D6 | Green | Bank 34, U1 | FPGA_LED |
| D7 | Green | 3.3V | PWR_LED |
Default PS MIO Mapping
| MIO | Function | Connected To | Notes |
|---|---|---|---|
| 0 | SDCARD | J10-9 | Card detect switch. |
| 1 | QSPI | U5-1 | SP0-CS |
| 2 | QSPI | U5-5 | SPI0-DQ0 |
| 3 | QSPI | U5-2 | SPI0-DQ1 |
| 4 | QSPI | U5-3 | SPI0-DQ2 |
| 5 | QSPI | U5-7 | SPI0-DQ3 |
| 6 | QSPI | U5-6 | SPI0-SCK |
| 7 | GPIO | U18-27 | USB PHY reset. |
| 10 | SDCARD | J10-7 | DAT0 |
| 11 | SDCARD | J10-3 | CMD |
| 12 | SDCARD | J10-5 | CLK |
| 13 | SDCARD | J10-8 | DAT1 |
| 14 | SDCARD | J10-1 | DAT2 |
| 15 | SDCARD | J10-2 | CD/DAT3 |
| 28 | USB-OTG | U18-7 | OTG-DATA4 |
| 29 | USB-OTG | U18-31 | OTG-DIR |
| 30 | USB-OTG | U18-29 | OTG-STP |
| 31 | USB-OTG | U18-2 | OTG-NXT |
| 32 | USB-OTG | U18-3 | OTG-DATA0 |
| 33 | USB-OTG | U18-4 | OTG-DATA1 |
| 34 | USB-OTG | U18-5 | OTG-DATA2 |
| 35 | USB-OTG | U18-6 | OTG-DATA3 |
| 36 | USB-OTG | U18-1 | OTG-CLK |
| 37 | USB-OTG | U18-9 | OTG-DATA5 |
| 38 | USB-OTG | U18-10 | OTG-DATA6 |
| 39 | USB-OTG | U18-13 | OTG-DATA7 |
| 48 | ESP | J5-2 | ESP_TXD |
| 49 | ESP | J5-7 | ESP_RXD |
| 52 | ESP | J5-6 | MOD_RST |
| 53 | ESP | J5-3 | ESP_GPIO0 |
Overview
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