Page History

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Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The 7 boot mode strapping pins on the TE0723 module are set to boot the system from quad SPI Flash only. ..For additional information refer to the TE0723 schematic and Xilinx UG585 Zynq-7000 All Programmable SoC Technical Reference Manual section "Boot Mode Pin Settings".

Signals, Interfaces and Pins

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JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through testpoints TP1-T4.

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JTAG Signal

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Testpoint

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Table 5: JTAG interface signalsFTDI USB/UART FIFO bridge connected to the J9 Micro USB connector.

Default PS MIO Mapping

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