Page History

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Following table describes how to set the control lines to configure the desired boot mode:

Table 11: Selectable boot modes

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Figure 8: TEBF0808 System Controller CPLDs

Programmable PLL Clock Generator and Reference Clock Oscillators

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Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected through I²C switch U16 between the Zynq module (master) and reference clock signal generator (slave).

Table 9: Pin description of PLL clock generator Si5338A

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Si5345 Si5338 OTP can only be programmed two times, as different user configurations may required different setup, TEBF0808 is normally shipped with blank OTP.
For more information Si5338 at SiLabs.

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The TEBF0808 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Table 10: Reference clock signal oscillators

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High-speed USB ULPI PHY

USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

Table 8: USB PHY interface connections

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On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

Table 7: Ethernet PHY interface connections

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I²C Switches

The I²C interface on B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as reference voltage.

The I²C bus works internally on module with reference voltage 1.8V, on the Zynq chip it is connected to the PS I²C interface via PS MIO bank 500, pins MIO10 and MIO11.

Table 9: MIO-pin assignment of the module's I²C interface

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I²C addresses for on-board devices are listed in the table below:

Table 10:  Module's I²C-interfaces overview

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An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

On-board LEDs

Table 14: LED's description

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 15: Maximum current of power supplies. *to be determined soon with reference design setup.

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There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:

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Figure 3: Power Distribution Diagram

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Following diagram clarifies the sequence of enabling the three power instances utilizing the DCDC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.

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Figure 4: Power-On Sequence Utilizing DCDC Converter Control Signals 

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See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 SoM.

Power Rails

Table 17: Power rails of the MPSoC module on accessible connectors

B2B connectors

Bank Voltages

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Table 18: Range of MPSoC module's bank voltages

B2B connectors

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Technical Specifications

Absolute Maximum Ratings

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Parameter

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Unit

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Notes / Reference Document

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Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

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Voltage on input pins of
NC7S08P5X 2-Input AND Gate

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Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

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TPS3106 data sheet,
VDD = LP_DCDC

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Storage temperature (ambient)

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-40

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°C

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Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Recommended Operating Conditions

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NC7S08P5X data sheet,
see schematic for VCC

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Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41

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TPS3106 data sheet,
VDD = LP_DCDC

Operating Temperature Ranges

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All dimensions are given in millimeters.

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Revision History

Hardware Revision History

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

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Document Change History

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