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The I/O signals are routed from the FPGA banks as LVDS-pairs to the connector.

Figure 23: FMC HPC Connector

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Table 23: FMC connector pin-outs of available MGT-lanes of the MPSoC

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Table 34: FMC connector pin-outs for reference clock output

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Table 45: FMC connector pin-outs of available interfaces to the System Controller CPLD

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Table 56:  Available VCCIO voltages on FMC connector

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Table 57:  MIO Assignment
On the carrier board there are up to

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

• 4 USB3.0

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• Superspeed ports (downward compatible to USB2.0

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• Highspeed)
• SDIO port with muxed MikroSD and MMC Card Socket
• Gigabit Ethernet interface connected per RGMII
• eMMC interface
• Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

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Figure 4: TEBF0808 MIO Interfaces

MPSoC's PS GT Bank 505 Interfaces

On the PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

• SATA (PS GT bank 505, MGT2 Lane)
• Display-Port (PS GT bank 505, MGT3 Lane, only TX-pair routed)
• PCI Express (PS GT bank 505, MGT0 Lane)
  
  

On the Upstream-side, this chip is connected to the MGT1 lane of MPSoC's PG GT bank 505 to establish the USB3.0 data lane. For the USB2.0 interface, the USB3.0 HUB U4 is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY U9 is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank 501.

Further interfaces of the MIO bank:

• SDIO port with muxed MikroSD and MMC Socket
• Gigabit Ethernet connected per RGMII
• eMMC Memory
• 4 x user configuration EEPROMs with I²C interface

Following block-diagram visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

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Figure 3: TEBF0808 MIO Interfaces

MPSoC's PS GT Bank 505 Interfaces

On the PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

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Table 68:  PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Figure 45: TEBF0808 PS GT Bank 505 Interface

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Table 69:  MGT Lane Assignment

Following block diagram show the wiring of the MGT lanes to the particular interface connectors:

Figure 56: TEBF0808 MGT Interfaces

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Table 710:  PMOD Pin Assignment

Figure 67: TEBF0808 CAN Interfaces, PMOD

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Table 811: PC compatible Headers

Figure 78: TEBF0808 PC Compatible Headers

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XMOD-Header J12 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U39.

Figure 89: TEBF0808 JTAG interfaces

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Table 1112: Selectable boot modes

In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. The current mode is set to boot from the QSPI Flash Memory.

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Both Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO and also Programmable Logic pins, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U17 and SC CPLD U39 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO) and , PL bank pins and I²C interface.

Figure 810: TEBF0808 System Controller CPLDs

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Table 913: Pin description of PLL clock generator Si5338A

Figure 911: Clocking Configuration of TE0808 SoM on TEBF0808 Carrier Board

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Table 1014: Reference clock signal oscillators

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Table 1115: USB PHY interface connections

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Table 1216: Ethernet PHY interface connections

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For this purpose, the TEBF0808 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.

Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches. 

The I²C bus works internally on-module with reference voltage 1.8V, it is connected to the PS I²C interface via PS MIO bank 501, pins MIO38 and MIO39, configured as master.

Table 1317: MIO-pin assignment of the module's I²C interface

I²C addresses for on-board slave devices are listed in the table below:

Table 1418:  On-board peripherals' I²C-interfaces device slave addresses

There are further I²C interfaces connected to the 8-channel I²C switches U16 and U27, which are provided by connectors with I²C interface. The I²C slave addresses depend on the devicedevices, which are attached to this connectors:

Table 1519:  On-board connectors' I²C-interfaces overview

Configuration EEPROMs

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

The TEBF0808 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:

Table 1620:  On-board configuration EEPROMs overview

4-port USB3.0 Hub

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

CAN FD Transceiver

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

eMMC Memory

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

24-bit Audio Codec

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

SDIO Port Expander

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank 501.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic)A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

DIP-swithches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

On-board LEDs

Table 14: LED's description

Power and Power-On Sequence

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The power-on sequence of the TE0808 SoM is managed by utilizing the SoM's DC-DC converter control signals ('Enable', 'Power-Good'), so the DC-DC converters of the SoM dedicated to the particular Power Domains of the Zynq Ultrascale+ MPSoC will be powerer-up in a specific sequence to meet the recommended criteria to power up the Xilinx Zynq Ultrascale+ MPSoC properly.

Figure 1012: TEBF0808 Power-Management

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There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:

Figure 1113: Power Distribution Diagram

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Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U17, which enables the particular on-board voltages.

Figure 1214: Power-On Sequence Utilizing DCDC Converter Control Signals

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