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Scroll Title
anchorFigure_OV_BD
titleTE0728 block diagram


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Main Components

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anchorFigure_OV_MC
titleTE0728 main components


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  1. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver  DP83848transceiver, U3
  4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
  5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
  6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
  7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
  8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
  9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
  10. 100 MBit Ethernet transceiver  DP83848MPHPEPtransceiver, U10
  11. 64 Kbit I2C EEPROM, 24LC64, U11
  12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
  13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
  14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
  15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
  16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
  17. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
  18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
  19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
  20. User LED Green

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Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

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Storage device name

Symbol

Content

Quad SPI Flash

U13

Empty

24xx64
EEPROMU11Not Programmed


Control Signals

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idComments
  • Overview of Boot Mode, Reset, Enables,

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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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VMIO1
FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM148(24)VCCO_1313variable from carrier
500JM143.3V
501J237VMIO1variable from carrier
33JM3343.3V
35JM3203.3V
35JM2223.3V501JM238MIO1 VREF is connected to resistor divider to support HSTL18


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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Scroll Title
anchorFigure_PWR_PS
titlePower On Sequence


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Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Dependencies


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The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

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Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
500VCCO_MIO0_5003.3V
501

VCCO_MIO1_500

3.3V
Variable
502VCCO_DDR_5021.5V
13 HRVCCO_13
3.3V
VariableSupplied by the carrier board. JM1
33 HR
VCCO_33
3.3V3.3VSupplied by carrier board. JM3
34 HR
VCCO_34
3.3V3.3V


35 HR
VCCO_35
3.3V3.3V

Supplied by the carrier board. JM2,JM3


Board to Board Connectors

Page properties
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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Include Page
PD:6 x 6 SoM LSHM B2B Connectors
PD:6 x 6 SoM LSHM B2B Connectors


6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

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