TE0728 TRM

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Overview

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

• • Xilinx XA7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
  • Temperature range: Automotive
  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • 16 MByte QSPI Flash memory (with XiP support)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
  • Evenly-spread supply pins for good signal integrity

Other assembly options for cost or performance optimization plus high volume prices available on request.

Depending on the customer design, additional cooling might be required.

Block Diagram

Main Components

1. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
3. 100 MBit Ethernet transceiver  DP83848, U3
4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
11. 64 Kbit I2C EEPROM, 24LC64, U11
12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
17. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
    
20. User LED Green

Initial Delivery State

Control Signals

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B).

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

MIO Pins

UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53.

On-board Peripherals

Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

RTC 

The RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.

EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

LEDs

DDR3 SDRAM

The TE0728 SoM has two 512 MByte volatile DDR3 SDRAM IC for storing user application code and data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

Low Dropout Linear Regulator

The low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.

Clock Sources

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power on Sequence

The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity. 

Power Distribution Dependencies

The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

Power Rails

Bank Voltages

Board to Board Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

• 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

  Operating Temperature:-55°C ~ 125°C
  Current Rating: 2.6A per ContactNumber of Positions: 80
  Number of Rows: 2

Technical Specifications

Absolute Maximum Ratings

Processing System(PS)

Programmable Logic(PL)

Recommended Operating Conditions

Temprature range: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 7 mm.

• PCB thickness: 1.6 mm.

Variants Currently In Production

Revision History

Hardware Revision History

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

Date	Revision	Contributor	Description
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Document change history.

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