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Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.

The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

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MIO3

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JTAG

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Table 12: Selectable boot modes

In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. The current mode is set to boot from the QSPI Flash Memory.

On-board Peripherals

System Controller CPDLs

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Si5338A (U35) InputSignal Schematic NameNote

IN1/IN2

CLK8_P, CLK8_N

Reference clock signal from Si5345 (CLK8 of prog. PLL on mounted SoM)

IN3

reference clock signal from oscillator SiTime SiT8008BI (U7)

25.000000 MHz fixed frequency.

IN4/IN6

pins put to GNDLSB (pin 'IN4') of the default I²C-adress 0x70 not activated.

IN5

not connected

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Si5338A (U35) Output
Signal Schematic NameNote

CLK0 A/B

SC_CLK0

Reference clock signal to SC CPLD U17 (single-ended signaling)

CLK1 A/B

SC_CLK1

Reference clock signal to SC CPLD U17 (single-ended signaling)

negative complementary signal 'SC_CLK1_N' put out to SMA Coax J33

CLK2 A/B

FMCCLK2_P, FMCCLK2_N

Clock signal routed to FMC connector J5, pins J5-K4 / J5-K5

CLK3 A/B

FMCCLK3_P, FMCCLK3_N

Clock signal routed to FMC connector J5, pins J5-J2 / J5-J3

Table 1312: Pin description of PLL clock generator Si5338A

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Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U10USB0_RCLK52.000000 MHzUSB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13ETH_CLK25.000000 MHzGigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7-25.000000 MHzQuad PLL clock generator U35, pin 3
DSC1123 oscillator, U23B505_CLK1150.0000 MHzPS GT Bank 505, dedicated for SATA interface

DSC1123 oscillator, U6

optional, not equipped

B505_CLK0100.0000 MHzPS GT Bank 505, dedicated for USB interface

Silicon Labs 570FBB000290DG, U45

optional, not equipped

B47_L5 (LVDS)250.MHzHD Bank 47 clock capable input pins
SiTime SiT8008BI oscillator, U25CLK_CPLD25.576000 MHzSystem Controller CPLD U35, pin 128

Table 1413: Reference clock signal oscillators

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PHY PinConnected toNotes
ULPIPS bank MIO52 ... MIO63Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK-52MHz from on board oscillator (U9)
REFSEL[0..2]-All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETBSC CPLD U17Low active USB PHY Reset (pulled-up to PS_1.8V).
DP, DM4-port USB3.0 Hub U4USB2.0 data lane
CPEN-External USB power switch active-high enable signal
VBUS5VConnected to USB VBUS via a series of resistors, see schematic
ID-For an A-device connect to the ground. For a B-device, leave floating

Table 1514: USB PHY interface connections

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PHY PinConnected toNotes
MDC/MDIOPS bank MIO76, MIO77-
PHY LED0..1SC CPLD U17, pin 67,86see schematic for details, forwarded to RJ45 GbE MagJack J7
PHY_LED2 / INTn:SC CPLD U17, pin 85Active low interrupt line
PHY_CLK125MSC CPLD U17, pin 70125 MHz Ethernet PHY clock out
CONFIGSC CPLD U17, pin 65Permanent logic high
RESETnSC CPLD U17, pin 62Active low reset line
RGMIIPS bank MIO64 ... MIO75Reduced Gigabit Media Independent Interface
SGMII-Serial Gigabit Media Independent Interface
MDIRJ45 GbE MagJack J7Media Dependent Interface

Table 1615: Ethernet PHY interface connections

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MIOSignal Schematic NameNotes
38I2C_SCL1.8V reference voltage
39I2C_SDA1.8V reference voltage

Table 1716: MIO-pin assignment of the module's I2C interface

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I²C Slave DevicesI²C Slave AddressSchematic Names of I²C Bus LinesI²C Switch
8-channel I²C switch U160x73I2C_SDA / I2C_SCL-
8-channel I²C switch U270x77I2C_SDA / I2C_SCL-
On-module Quad programmable PLL clock generator Si53450x69PLL_SDA / PLL_SCLU27
Configuration EEPROM U240x54MEM_SDA / MEM_SCLU16
Configuration EEPROM U360x52MEM_SDA / MEM_SCLU16
Configuration EEPROM U410x51MEM_SDA / MEM_SCLU16
Configuration EEPROM U220x50MEM_SDA / MEM_SCLU16
8-bit I²C IO Expander U440x26SFP_SDA / SFP_SCLU16
24-bit Audio Codec U30x38A_I2C_SDA / A_I2C_SCLU27
USB3.0 Hub configuration EEPROM U50x51USBH_SDA / USBH_SCLU16
USB3.0 Hub0x60USBH_SDA / USBH_SCLU16
8-bit I²C IO Expander U380x27MEM_SDA / MEM_SCLU16
On-board Quad programmable PLL clock generator U35 Si53380x70MCLK_SDA / MCLK_SCLU16
8-bit I²C IO Expander U340x24FF_E_SDA / FF_E_SCLU27
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL)User programmableSC_SDA / SC_SCLU27
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL)User programmableI2C_SDA / I2C_SCL-

Table 1817:  On-board peripherals' I2C-interfaces device slave addresses

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ConnectorSchematic Names of I²C Bus LinesI²C Switch
PCIe Connector J1PCIE_SDA / PCIE_SCLU16
SFP+ Connector J14ASFP1_SDA / SFP1_SCLU16
SFP+ Connector J14BSFP2_SDA / SFP2_SCLU16
FireFly Connector J15FFA_SDA / FFA_SCLU27
FireFly Connector J22FFB_SDA / FFB_SCLU27
FMC Connector J5FMC_SDA / FMC_SCLU16
PMOD Connector P1PMOD_SDA / PMOD_SCLU27
PMOD Connector P3EXT_SDA / EXT_SCLU27

Table 1918:  On-board connectors' I2C-interfaces overview

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EEPROM ModellSchematic DesignatorMemory DensityPurpose
24LC128-I/STU24128 Kbituser
24AA025E48T-I/OTU362 Kbituser
24AA025E48T-I/OTU412 Kbituser
24AA025E48T-I/OTU422 Kbituser
24LC128-I/STU5128 KbitUSB3.0 Hub U4 configuration memory

Table 2019:  On-board configuration EEPROMs overview

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There are two 4 bit DIP Switches on the TEBF0808 , they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

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carrier board to configure options and set parameters. The table below describes the functionalities of the particular switches:

DIP-switch S4Position ONPosition OFFNotes
S4-1PUDC_B is LowPUDC_B is HIGHInternal pull-up resistors during configuration are enabled at ON-position.
I/O's are 3-stated until configuration of the FPGA completes. 
S4-2xxnot connected
S4-3SC CPLDs' JTAG enabledSC CPLDs' JTAG disabledJTAG interface is enabled on both SC CPLDs, as this CPLDs are configured in a casdaced JTAG chain
S4-4DC-DC converter U18 (5V) enabledDC-DC converter U18 (5V) not manually enabledIn OFF-position, the DC-DC-converter will be still enabled by the control signals of SC CDPD U17

Table 20: DIP-switch S4 functionality description

DIP-switch DIP Switch S5 located close to PWR push-button . This DIP Switch is connected to the two baseboard control CPLD's.System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The switches of this DIP-switch have to be set in bit-patterns to set a parameter like boot mode or FMC_VADJ value:

S5-1S5-2S5-3S5-1234Description
ONONONONDefault, boot from SD/eMMC, 1.8V FMC VADJ
ONONxxBoot from microSD, SD or SPI Flash
OFFONxxBoot from eMMC
ONOFFxxBoot mode  PJTAG0
OFFOFFxxBoot mode main  JTAG
xxxONFMC VADJ = 1.8V
xxxOFFFMC VADJ = 1.2V

 Table 21: DIP-switch S4 functionality description

On-board LEDs

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LED

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The TEBF0808 carrier board is equipped with several LED to signal current states and activities. The functionality of the LEDs D4 ... D7 depends on the current firmware of the SC CPLDs U17 and U39.

LEDColorDescription and Notes
D4greenStatus LED, connected to SC CPLD U17
D5redStatus LED, connected to SC CPLD U17
D6greenStatus LED, connected to SC CPLD U39
D7redStatus LED, connected to SC CPLD U39
D1redSFP+ interface status LED, connected to SC CPLD U17
D8greenSFP+ interface status LED, connected to SC CPLD U17
D9redSFP+ interface status LED, connected to SC CPLD U17
D10greenSFP+ interface status LED, connected to SC CPLD U17
D17green

LED is on if all USB3.0 and USB 2.0 ports are in the suspend state and is
off when either of the ports comes out of the suspend state.

Table 22: On-board LEDs functionality description

Table 14: LED's description

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Power and Power-On Sequence

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