Versions Compared

Old Version 18

changes.mady.by.user Ali Naseri

Saved on

compared with

New Version 19

changes.mady.by.user Ali Naseri

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

HeaderPin NameFunctionConnected toNotes
J10

Pin 1, HD LED+
Pin 3, HD LED-
Pin 2, PWRLED+
Pin 4, PWRLED-
Pin 5, GND
Pin 7, RSTSW
Pin 6, PWRSW
Pin 8, GND
Pin 9, +5V DC

HD LED Anode
HD LED Cathode
Power LED Anode
Power LED Cathode
Ground
Reset Switch
Power Switch
Ground
5V DC Supply

SC CPLD U39Reset und Power Switch-pins are also
connected to switch button S1
also connected to switch button buttons S1 and S2
J9

Pin 1, PORT1L
Pin 3, PORT1R
Pin 9, PORT2L
Pin 5, PORT2R
Pin 7, SENS_SEND
Pin 2, GND

Microphone Jack Left
Microphone Jack Right
Audio Out Jack Left
Audio Out Jack Right
Jack Detect / Mic in
Ground		24-bit Audio Codec IC U3-
J23Pin 1, 3V3SB
Pin 4, S1		3.3V DC Supply
PC compatible Beeper		SC CPLD U39-
J26

Pin 1, GND
Pin 2, 12V
Pin 3, F1SENSE
Pin 4, F1PWM

Ground
12V DC Supply
RPM
PWM		SC CPLD U394-wire PWM FAN connector
J35

Pin 1, GND
Pin 2, 12V
Pin 3, F2SENSE
Pin 4, F2PWM

Ground
12V DC Supply
RPM
PWM		SC CPLD U39

4-wire PWM FAN connector

optional load switch U48 to turn off/on FAN
with pin F2_EN

J19

Pin 1, GND
Pin 2, 5V

Ground
5V DC Supply		Load Switch Q3 (5V DCDC)2-wire FAN connector

Fan off/on switchable by signal 'FAN_FMC_EN'
on SC CPLD U39

...

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller CPDLs

The TEBF0808 is equipped with two System Controller CPLDs with the schematic designators U17 and U39. The CPLDs are provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family).

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Image Added

 

 

Power and Power-up Sequence

Image Added