Page History

...

1. 5V barrel jack, J12
2. RJ-45 Gigabit Ethernet MegJack, J3
3. RJ-45 10/100-BaseT Ethernet MegJack, J4
4. RJ-45 10/100-BaseT Ethernet MegJack, J5
5. VG96 connector placeholder, J9
6. XMOD (TE0790) header, JB3
7. 2-pin header for VBAT-IN supply-voltage, J2
8. 2x6 pin header for setting VCCIO_33, J6
9. 2x6 pin header for setting VCCIO_13, J7
10. MicroSD Card socket, J1
11. Red LED, D1
12. Push Button, S1
13. Micro USB2.0 B Receptacle
14. VG96 connector placeholder, J8
15. B2B Connector, JB1
16. B2B Connector, JB2
17. 4-bit DIP-switch, S2

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

...

Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:

Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

...

Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals  connected to the VG96 connectors.

...

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip on the mounted SoM can be programed via USB2.0 interface.

Table 4: JTAG interface signals.

...

UART interface is available on B2B connector JB2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

Table 5: UART interface signals.

...

Two I²C interfaces are provided on B2B connector JB2. I²C0 interface is connected to the Configuration EEPROMs U1 and U2 and is dedicated to these on-board peripherals. Interface I²C1 is routed to the VG96 connector J9 and is available to the user for general purposes:

Table 6: I²C interface signals.

...

The SD IO interface of the SoM's Zynq chip (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip can be booted from an inserted MicroSD Card:

Table 7: SD IO interface signals.

...

Following table gives an overview of the USB2.0 interface signals:

Table 8: USB2.0 interface signals and connections.

...

The TEB0729 Carrier Board is fitted with one RJ-45 Gigabit Ethernet Magnetic jack J3. The MegJack has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the B2B connector JB2, where they can be accessed by the GbE PHY transceiver of the mounted SoM:

Table 9: GbE interface signals and connections.

For the same GbE transceiver PHY on the mounted SoM, on the Carrier Board is also a SGMII (Serial Gigabit Media Independent Interface) available. The SGMII pins are available on VG96 connector:

Table 10: GbE SGMII signals and connections.

...

The TEB0729 Carrier Board is also fitted with two additional RJ-45 MegJacks providing 10/100-BaseT Ethernet interfaces. This interfaces are routed to the B2B connector JB2

Table 11: 10/100-BaseT Ethernet interfaces signals and connections.

...

Following table describes the signals and interfaces of the XMOD header JB3:

Table 12: XMOD header signals and connections.

...

Table below describes DIP-switch S2 settings for configuration of the mounted SoM:

Table 13: DIP-Switch S2 SoM configuration settings.

...

Following table describes how to configure the VCCIO of the SoM's banks with jumpers:

Table 14: VCCIO jumper settings.

...

The Carrier Board's push button S1 is connected to the 'NRST_IN' signal of the mounted SoM. The function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.

On-board LEDs

Table 15: On-board LEDs.

Power and Power-On Sequence

...

The maximum power consumption of a module mainly depends the Carrier Board depends mainly on the mounted SoM's FPGA design running on the FPGAZynq chip.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 16: Typical power consumption.

...

Figure : Module power-on diagram.

Power Rails

Table 17: Power pin description of B2B Module Connector.

Table 18: Power Pin description of VCCIO selection jumper pin header.

Table 19: Main Power jack and pins description.

Table 20: Power pin description of peripheral connector.

Table 21: Power pin description of XMOD/JTAG Connector.

...

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

...

Recommended Operating Conditions

Table : Module recommended operating conditions.

...

Hardware Revision History

Table : Module hardware revision history.

...

<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

Table : Document change history.

...