Overview

 This page showcases important details of the module-carrier combination TEG2000 + TE0703 and introduces the available script-based test designs to get the board up and running.
Note that some connectors on the carrier board like the RJ45 or the USB Connector cannot easily be implemented in a design due to the missing PHY. For that application a carrier like TEB0707  with CRUVI adapters would be more appropriate.

Requirements

Getting Started with the TEG2000 + TE0703

The module TEG2000 has Cologne Chip GateMate A1 FPGA onboard that allows you to create extensive digital hardware designs.

Most of the FPGA IOs are spread arround the carrier. The TEG2000 is assembled with a QSPI non-volatile Flash memory(128 Mbit) and plenty of IOs which enable great hardware expandability. For communication and configuration the carrier offers a JTAG/UART Interface. 

 Official Documentation

• Link to the shop: 
  • https://shop.trenz-electronic.de/de/TEG2000-01-P001-FPGA-Modul-mit-GateMate-A1-von-Cologne-Chip-16-MByte-QSPI-Flash-4-x-5-cm
• Technical Reference Manual:
  • coming soon.
• Online Resources & Reference Designs:
  • official cologne chip documentation(possibly login needed):
    https://colognechip.com/programmable-logic/gatemate/
  • colognechip test design: https://colognechip.com/downloads/cc-toolchain-win.zip
    
  • Comprehensive video on the toolchain installation and usage: https://www.youtube.com/watch?v=lMUQplZXPoM

TEG2000 module + TE0703 carrier - Hardware Features

• FPGA
  • Cologne Chip GateMate CCGM1A1 FPGA
• Clocking
  • 25 MHz clock from clocking chip SiT8008 on TEG2000 module
• Memory
  • 16 MByte Quad-SPI Flash
• Communication
  • On carrier USB-JTAG/UART
• Connectors
  • B2B connector - Module(JM1&JM2) to Carrier(JB1&JB2)
  • Unpopulated PIN Header on carrier(J1 & J2)
• Configuration and Debug
  • On carrier USB-JTAG interface
• Jumper
  • Adjustable BANK34 supply voltages VCCIOA, VCCIOC ,VCCIOD (max. 2,7V)
    
• General Purpose I/O
  • D2 user LED on module (green)

 TEG2000 + TE0703 Hardware Blockdiagram

 Basic IOs<->FPGA connections are as following, Table 1:

Board Power-Up

 TEG2000 + TE0703 Hardware Setup and Power up

1. Before connecting the Board to the PC, make sure to properly mount the module TEG2000 onto the carrier TE0703 via the B2B connector. It can only fit one way around.

2. Check the Jumper settings. Bank Voltages to 1.8V. Caution! 3.3V setting could destroy the module. The description of the DIP-switches on the carrier can be found here.
   
   

3. Use a Mini USB Cable to connect via USB to PC and a DC cable to connect to a power supply. The carrier TE0703 is supplied with 5V and 1A on the current limitation should suffice.
4. Turning the board on, the LED D2 might be blinking if the module comes with a preloaded design. Otherwise the red DONE LED D3 would be ON if no FPGA design is loaded.
5. The FPGA can be programmed with one of the example designs from cologne chip following the user guide ug1002 → Quick start. To be able to programm program and communicate over use UART with the board, you need to install the right driver for the FTDI device on the carrier with the following zadig software. 
   

   Expand
   title zadig driver installation
   For the programmer to work you need the zadig software https://zadig.akeo.ie/ Download the exe file Execute it and click on Options → List all devices. Then Options → Ignore Hubs or Composite Parents From the device list choose the Digilent USB Device interface 0 / TE0703 device interface 0. Then select libusb-win32 any version and replace the driver for one interface only! After that, you should see your device in the device manager as follows: You can return the device to normal by deleting the driver.

6. If the QSPI Flash is loaded with our philosopher test design the green led should blink and you can connect to the board with a program like SmarTTY. Just open up SmarTTY and connect to with baud-rate of 115200. You may need to press the reset button to see the output.