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Note |
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JTAGEN pin in JM1 should be kept low or grounded for normal operation. |
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Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 MHz | U14 | PS_CLK | PS Subsystem main clock |
10/100/1000 Mbps ETH PHY reference | 25 MHz | U10 | - | |
USB PHY reference | 52 MHz | U12 | - |
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Peripheral | IC | Designator | PS | MIO | Notes | ||||||
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EEPROM I2CU8 | 24AA025E48T-I/OT | U8 | I2C0 | MIO10, MIO11 | MAC1-Adress | ||||||
EEPROM I2C | U9 | 24AA025E48T-I/OT | U9 | I2C0 | MIO10, MIO11 | MAC2-Adress | |||||
EEPROM I2C | U20 | 24AA025E48T-I/OT | U20 | I2C0 | MIO10, MIO11 | MAC3-Adress | |||||
RTC | ISL12020MIRZ | U22 | I2C0 | MIO10, MIO11 | Temperature compensated real time clock | ||||||
RTC Interrupt | ISL12020MIRZ | U22 | GPIO | MIO46 | Real Time Clock Interrupt | ||||||
SPI Flash | Clock PLL | ||||||||||
Ethernet | |||||||||||
USB | |||||||||||
LED | |||||||||||
USB Reset | |||||||||||
Ethernet Reset |
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