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Product Specification

Port Description

NameDirectionPinDescriptionPCB REV2 Exception
C_T1 24/ currently_not_usedNC
C_T2 26/ currently_not_usedNC
C_T3 25/ currently_not_usedNC
C_TCK         131JTAG J28 (XMOD2) / internal currently_not_used
 
C_TDI         136JTAG J28 (XMOD2) / internal currently_not_used 
C_TDO1        137JTAG J28 (XMOD2) / internal currently_not_used 
C_TMS         130JTAG J28 (XMOD2) / internal currently_not_used 
CAN_FAULT    in106CAN / currently_not_used 
CAN_RX       in107CAN / currently_not_used 
CAN_S        out105CAN / currently_not_used 
CAN_TX       out104CAN / currently_not_used 
CLK_125MHZ / PHY_CLKin70/ currently_not_used 
CON_NTRST     117/ currently_not_used 
CON_RTCK / JTAG_RTCK    out125JTAG, Connector J30 
CON_SRST / JTAG_SRSTin127JTAG, Connector J30 
CON_TCK / JTAG_TCKin122JTAG, Connector J30 
CON_TDI / JTAG_TDIin119JTAG, Connector J30 
CON_TDO / JTAG_TDOout126JTAG, Connector J30 
CON_TMS / JTAG_TMSin121JTAG, Connector J30 
DIR_T1 23/ currently_not_usedNC
DIR_T2 28/ currently_not_usedNC
DIR_T3 27/ currently_not_usedNC
DP_AUX_DE   / DP_DE out92Display Port 
DP_AUX_RX   / DP_RXin91Display Port 
DP_AUX_TX    / DP_TXout93Display Port 
DP_EN        out77Display Port 
DP_TX_HPD  /DP_HDP in94Display Port 
ETH_RST      out62Ethernet 
EX_IO1        112PMOD / currently_not_used 
EX_IO2        113PMOD / currently_not_used 
EX_IO3        114PMOD / currently_not_used 
EX_IO4        115PMOD / currently_not_used 
F2_EN         19FAN J35 / currently_not_usedNC
F2PWM         20FAN J35 / currently_not_usedNC
F2SENSE       21FAN J35 / currently_not_usedNC
FMC_CLK_DIR  in73FMC 
FMC_TCK      out95FMC 
FMC_TDI      out96FMC 
FMC_TDO      in97FMC 
FMC_TMS      out98FMC 
FMC_VID0     out139FMC VADJ Power Selection 
FMC_VID1     out140FMC VADJ Power Selection 
FMC_VID2     out141FMC VADJ Power Selection 
GND 84REV03 unconnected / currently_not_usedUSB_TRST, other USB HUB
HDIO_SC10 / SC10 inout60FPGA / DP_RX/DP_RX or 'Z' 
HDIO_SC11 / SC11  in59FPGA / DP_DE 
HDIO_SC12 / SC12out58FPGA / DP_HPD 
HDIO_SC13 / SC13out57FPGA / RGPIO TX 
HDIO_SC14 / SC14  in56FPGA / RGPIO RX 
HDIO_SC15 / SC15in55FPGA / RGPIO CLK 
HDIO_SC16     54FPGA /  currently_not_used 
HDIO_SC17     52FPGA /  currently_not_used 
HDIO_SC18 / SC18in68
 
FPGA / currently_not_used 
HDIO_SC19 / SC19in69FPGA /  currently_not_used 
I2C_RST      out61
 
I2C 
JTAGENB       120external Pin for CPLD Firmware Update  
LED_1A / JLED1out109
 
USB3.0 LED Jellow 
LED_2A / JLED2Aout111
 
USB3.0 LED Green/Orange 
LED_2B / JLED2Bout110
 
USB3.0 LED Green/Orange 
MIO26        in41
 
MIO / currently_not_used 
MIO27        in40
 
MIO / currently_not_used 
MIO28        in39
 
MIO / currently_not_used 
MIO29        in38
 
MIO / currently_not_used 
OCLK_EN  / OSC_EN   out74
 
Programmable Oscillator U45 
PHY_CONFIG   out65
 
ETH PHY 
PHY_LED0     in67
 
ETH PHY 
PHY_LED1     in86
 
ETH PHY 
PHY_LED2     in85
 
ETH PHY 
SC_CLK0 / CLK0    in76/ currently_not_usedSC_CLK_P
SC_CLK1 / CLK1    in75/ currently_not_usedSC_CLK_N
SC_IO0 / X0in50
 
Master-Slave SC-Communication / Power Reset 
SC_IO1 / X1      in49
 
Master-Slave SC-Communication / Power Reset 
SC_IO2 / X2in48
 
Master-Slave SC-Communication / currently_not_used 
SC_IO3 / X3in47
 
Master-Slave SC-Communication / currently_not_used 
SC_IO4  / X4    out45
 
Master-Slave SC-Communication / currently_not_used 
SC_IO5 / X5     out44
 
Master-Slave SC-Communication / currently_not_used 
SC_IO6 / X6out43Master-Slave SC-Communication / Sanity check to other CPLD (FMC VADJ Enable) 
SC_IO7 / X7out42Master-Slave SC-Communication / Sanity check to other CPLD (FMC VADJ Enable) 
SC_IO8        22Master-Slave SC-Communication / currently_not_usedNC
SC_SCL  / SCL    in14
 
I2C Mux U27 / currently_not_used 
SC_SDA / SDA      in13
 
I2C Mux U27 / currently_not_used 
SC2_SW3 / SW3    in6
 
DIP-Switch S5-3 
SC2_SW4 / SW4    in5
 
DIP-Switch S5-4 
SD_WP        in100
 
MMC SD / currently_not_used 
SFP_LED1 / SFP_LED0out81
 
SFP 
SFP_LED2 / SFP_LED1out82
 
SFP 
SFP_LED3 / SFP_LED2out78
 
SFP 
SFP_LED4 / SFP_LED3out83
 
SFP 
SFP1_LOS      32SFP / currently_not_usedNC, controlled by FPGA
SFP1_TX_DIS  out33
 
SFPNC, controlled by FPGA
SFP2_LOS      35SFP / currently_not_usedNC, controlled by FPGA
SFP2_TX_DIS  out34
 
SFPNC, controlled by FPGA
STAT_LED0 / LED0 99
/ currently_not_used
LED D4 Green  
STAT_LED1 / LED1 128
/ currently_not_used
LED D1 Red  
USB0_RST / USB_RST   out71USB (U9) PHY Reset
also
USB PHY and HUB Reset
USBH_LED_G3   11USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_G4   12USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_SS1  9USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_SS2 / dummyout133USB Hub (U4) Dummy Signal / currently_not_usedNC, other USB HUB
USBH_LED_SS3  132USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_LED_SS4  138USB Hub (U4) / currently_not_usedNC, other USB HUB
USBH_MODE0   out142
 
USB Hub (U4)NC, other USB HUB
USBH_MODE1   out143
 
USB Hub (U4)NC, other USB HUB
USBH_RST     out10
 
USB Hub (U4)NC, other USB HUB
XMOD1_A       3J12 (XMOD 2) / currently_not_used 
XMOD1_B       2J12 (XMOD 2) / currently_not_used 
XMOD1_E      out4
 
J12 (XMOD 2 LED) 
XMOD1_G      in1
 
J12 (XMOD 2 Button) 

 

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

Power

FMC VADJ is 1.8V if S5-4 is ON .

JTAG Signal

Power

Reset

RGPIO

LED

...

else 1.2V.

Reset

Main Reset is send by Slave CPLD via X0, X1 Pins.

USB PHY hold ~0,6s after Main Reset or XMOD_G Reset or inv.RGPIO Bus Pin 0 (if active).

USB HUB hold ~0,25s after Main Reset or XMOD_G Reset or inv. RGPIO Bus Pin 0 (if active). Long delay is a BUGFIX: is currently need to start Linux before Reset is disabled.

I2C Reset is Main Reset  or inv. RGPIO Bus Pin 2 (if active).

ETH Reset is  Main Reset  or inv. RGPIO Bus Pin 3 (if active).

Enable

FMC VADJ Enable is set from Slave CPLD via Saity Check (X6, X7).

SFP1 and SFP2 are always enabled.

USB

USB Hub Device Operation Mode (USBH_MODEx Pins) are set to internal ROM configuration. Can be controlled by RGPIO Bus Pin 4 and 5.

ETH

PHY Address is 1.

RGPIO

 

LED

NameDescription
LED0 D4 GreenRGPIO (6) when active else USB HUB RSTN
LED1 D1 RedRGPIO (7) when active else Main Reset from Slave CPLD
  

 

Appx. A: Change History and Legal Notices

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Older Revision (PCB REV03) to REV04

  • BUGFIX PCIe Reset PinFix USB HUB Mode default state over RGPIO

Older Revision (PCB REV02) to REV04

  • Add all functionality from Older older Revision (PCB REV03)

Document Change History

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