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<!-- Components on the Module, like Flash, PLL, PHY... --> |
The CAN bus is routed to screw terminal J2.
PIN | Signal | B2B |
---|---|---|
J2-1 | CAN0_N | J1-1 |
J2-2 | GND | |
J2-3 | CAN0_P | J1-3 |
The module has the following reference clock signals provided by on-board oscillators:
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Table 11: On-board Push Buttons.
Pin Header J6
J6-2
provides access to power functions, bootmode selection and PMIC In-Circuit Programming.
PIN | Signal | B2B |
---|
J6-1 |
VIN | J1- |
154, J1-156, J1-158, J1-160 |
J6-2 |
VIN | J1-154, J1-156, J1-158, J1-160 |
J6- |
3 |
GND |
J6- |
PS MIO user button, pulled up, on push de-asserted
For voltage selection VCCIO_35 of Bank 35 other than 3.3V the header J19 can optionaly assambled. Therefore 0 Ohm resistor R45 has to be removed!
4 | GND | |
J6-5 | I2C_SCL | J1-142 |
J6-6 | VBAT | J1-152 |
J6-7 | I2C_SDA | J1-144 |
J6-8 | PWR_GPIO2 | J1-143 |
J6-9 | ONKEY | J1-148 |
J6-10 | PWR_GPIO4 | J1-141 |
J6-11 | PWR_TP | J1-146 |
J6-12 | RESETREQ | J1-150 |
J6-13 | MODE0 | J1-2 |
J6-14 | GND | |
J6-15 | MODE1 | J1-4 |
J6-16 | GND |
Table 12: Pin Header J6.
For voltage selection VCCIO_35 of Bank 35 other than 3.3V the header J19 can optionaly assembled. Therefore 0 Ohm resistor R45 has to be removed!
PIN | Signal | B2B |
---|---|---|
J19-1 | VLDO1 | J1-83 |
J19-2 | GND | |
J19-3 | VCCIO_35 | J1-54 |
J19-4 | VLDO2 | J1-94 |
J19-5 | VLDO34 | J1-53 |
J19-6 | GND |
Table 13: Optional Pin Header J19.
Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes. Description follows below.
PL Button and LED IOs are additionally routed to optionally assembled pin header J8.
PIN | Signal | B2B |
---|---|---|
J8-1 | 3.3V | J1-43, J1-74 |
J8-2 | GND | |
J8-3 | S4 | J1-126 |
J8-4 | S2 | J1-124 |
J8-5 | ULED5 | J1-130 |
J8-6 | ULED6 | J1-128 |
J8-7 | ULED3 | J1-134 |
J8-8 | ULED4 | J1-132 |
J8-9 | ULED1 | J1-138 |
J8-10 | ULED2 | J1-136 |
Table 14: Optional Pin Header J8.
Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.
PIN | Signal | B2B |
---|---|---|
J7-1 | 3.3V | 43, 74 |
J7-2 | GND | |
J7-3 | GND | |
J7-4 | MIO8 | J1-14 |
J7-5 | MIO10 | J1-31 |
J7-6 | MIO11 | J1-33 |
J7-7 | MIO12 | J1-35 |
J7-8 | MIO13 | J1-37 |
J7-9 | MIO14 | J1-39 |
J7-10 | MIO15 | J1-41 |
Table 15: Optional Pin Header J7.
Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.
PIN | Signal | B2B |
---|---|---|
J9-1 | 1.8V | J1-63 |
J9-2 | GND | |
J9-3 | GND | |
J9-4 | MIO_46 | J1-32 |
J9-5 | MIO_50 | J1-40 |
J9-6 | MIO_PB | J1-42 |
Table 16: Optional Pin Header J9.Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B, especially for testing and extension purposes.
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Power Input | Typical Current |
---|---|
VIN | TBD* |
Table 1217: Typical power consumption.
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Power Rail Name | B2B J1 Pins | Direction on B2B | Notes |
---|---|---|---|
VIN | 154, 156, 158, 160 | Output | External main supply voltage. |
3.3V | 43, 74 | Input | |
1.8V | 63 | Input | |
VCCIO_35 | 54 | Output | |
VLDO1 | 83 | Input | |
VLDO2 | 94 | Input | Used to enable UART level shifter. Therefore fix at 1.8V. |
VLDO34 | 53 | Input | |
VBAT | 152 | Input/Output | Reserved for PMIC backup battery and charger. |
Table 12 18 : Board power rails.
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Order | REF Number | Samtec Number | Type | Mated Height | Data sheet | Comment |
---|---|---|---|---|---|---|
- | REF-192552-01 | SS5-80-3.50-L-D-K-TR | Baseboard connector | 4 mm | http://suddendocs.samtec.com/catalog_english/ss5.pdf | Standard connector used on board |
27220 | REF-192552-02 | ST5-80-1.50-L-D-P-TR | Module connector | 4 mm | http://suddendocs.samtec.com/catalog_english/st5.pdf | Standard connector used on module |
Table 1519: Connectors for module and base board.
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Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | V | - | ||
Storage temperature | °C | - |
Table 20: Board absolute maximum ratings.
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Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | ||||
Operating temperature |
Table 21: Board recommended operating conditions.
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Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
- | 01 | Prototypes |
Table 22: Module hardware revision history.
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Date | Revision | Contributors | Description | ||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| ||||||||||||||||||
2018-07-02 | v.1 | Initial document. |
Table 23: Document change history.
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