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The Trenz Electronic TEB0724-01 ... is an industrial-grade ... module ... based on Xilinx ...is a carrier board for the TE0724 and compatible modules.

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Refer to http://trenz.org/te0720teb0724-info for the current online version of this manual and other available documentation.

Key Features

• Samtec 160 pin board to board connector
• 10x 2x6 Pin  Pin Pmods, (4 8 usable as dual PmodPmods, 1x single Pmod, 1x I²C PMODPmod)
• MicroUSB to JTAG/UART bridge
• CAN screw terminal
• RJ45 Gigabit Ethernet MagJack connector
• 6x LED, 2x Push Button Buttons on FPGA
• 1 LED and 1 Push button Button on PS
• Power and Reset  Reset Push Buttons
• On-board Power Protection Circuit and Power on LED
  
  

Block Diagram

put block diagram here ... like example block diagram below

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Main Components

Put top and bottom pics with labels of the real PCB here... like example diagram below

Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State

Table 1: TE0724-01 main components.

Initial Delivery State

Not programmed.

Table 1: Initial delivery state of programmable devices on the module.

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By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

Table 2: Selecting power-on boot device.

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I/O signals connected to the SoCs I/O bank and B2B connector: 

Table x: General overview of PL I/O signals connected to the B2B connectors.

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

Table x: MGT reference clock sources.

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JTAG access to the ... is provided through B2B connector .... 

Table 5: JTAG interface signals.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table x: System Controller CPLD I/O pins.

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Note that table column says "Signal Name", it should match the name used on the schematic.

Table x: Quad SPI interface signals and connections.

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Describe SD Card interface  shortly here if the module has one...

Table x: SD Card interface signals and connections.

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On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

Table x: ...

USB Interface

USB PHY is provided with ...

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

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On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

Table x: I²C slave device addresses.

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table : Programmable quad PLL clock generator inputs and outputs.

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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table : Reference clock signals.

On-board LEDs

Table : On-board LEDs.

Power and Power-On Sequence

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table : Typical power consumption.

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NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Table : Module power rails.

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Bank Voltages

Table : Module PL I/O bank voltages.

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Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

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Recommended Operating Conditions

Table : Module recommended operating conditions.

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Hardware Revision History

Table : Module hardware revision history.

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v.58

Table : Document change history.

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