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Overview
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This tutorial guides you from initaltest_board reference design for TE0821 SoM to custom extensible vitis platfom and then shows how to implement and run basic VADD example on 2cg module No. 1. Next, Vitis AI 2.0 BSP for large TE0821 4ev module No. 8 is created from module No. 1 files. Vitis-AI 2.0 dpu_trd example (ResNet50) running on DPU is compiled for the TE0821 4ev module No. 8.
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Key Features
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Requirements
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General Chapter Vitis AI Prepare Development Environment is included |
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Prepare Reference Design for Extensible Custom Platform
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Update Vivado Project for Extensible Platform
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Trenz Electronic Scripts allows posibility change some setup via enviroment variables, which depends on the used OS and PC performace. To improve performance on multicore CPU add global envirment on line 64: to /etc/bash.bashrc or local to design_basic_settings.sh For othervariables see also: |
In Ubuntu terminal, source paths to Vitis and Vivado tools by
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$ source /tools/Xilinx/Vitis/2021.2/settings64.sh |
Download TE0821 test_board Linux Design file (see Reference Design download link on chapter Requirements) with pre-build files to
~/Downloads/TE0821-test_board-vivado_2021.2-build_20_20221107115647.zip
This TE0821test_board ZIP file contains bring-up scripts for creation of Petalinux for range of modules in zipped directory named “test_board”.
Unzip the file to directory:
~/work/TE0821_01_240
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| All supported modules are identified in file: ~/work/TE0821_01_240/test_board/board_files/TE0821_board_files.csv |
We will select module 01 with name TE0821-01-2AE31KA, with device xczu2cg-sfvc784-1-e on TE0706-03 carrier board. We will use default clock 240 MHz.
That is why we name the package TE0821_01_240 and proposed to unzip the TE0821-test_board Linux Design files
TE0821-test_board-vivado_2021.2-build_20_20221107115647.zip
into the directory:
~/work/TE0821_01_240
In Ubuntu terminal, change directory to the test_board directory:
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$ cd ~/work/TE0821_01_240/test_board |
Setup thetest_board directory files for a Linux host machine.
In Ubuntu terminal, execute:
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$ chmod ugo+rwx ./console/base_sh/*.sh $ chmod ugo+rwx ./_create_linux_setup.sh $ ./_create_linux_setup.sh |
Select option (0) to open Selection Guide and press Enter
Select module variant 1 from the selection guide, press enter and agree selection
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Module No. 01: TE0821-01-2AE31KA (zu02cg-1e-4gb) is selected.
Create Vivado Project by typing 1
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Vivado project for module No. 01: TE0821-01-2AE31KA (zu02cg-1e-4gb) will be generated.
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Selection Guide automatically modified ./design_basic_settings.sh with correct variant, so other provided bash files to recreate or open Vivado project again can be used later also. In case of using selection guide, variant can be selected also manually:
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The Vivado tool will be opened and Trenz Electronic HW project for the TE0821-test_board Linux Design, part 01 will be generated.
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In Vivado window Sources, click on zusys_wrapper and next on zusys.bd to open the HW diagram in IP integrator:
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It is possible to display diagram in separate window by clicking on float icon in upper right corner of the diagram.
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Zynq Ultrascale+ block is configured for the Trenz TE0821-test_board Linux Design on the TE0706-03 carrier board.
This is starting point for the standard PetaLinux system supported by Trenz with steps for generation of the PetaLinux system. Parameters of this system and compilation steps are described on Trenz Wiki pages:
https://wiki.trenz-electronic.de/display/PD/TE0821+test_board
Follow steps described in these wiki pages if you would like to create fixed, not extensible Vitis platform.
The Extensible Vitis platform generation steps are described in next paragraphs.
Create Extensible Vitis platform
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To implement hardware this tutorial offers two alternatives: Fast Track or Manual Track:
- Choose Fast Track to use TCL script to do the same modifications as in manual track case automatically,
- Select Manual Track path if you want to see all required hardware modifications required for custom platform.
Fast Track
Block Design of the Vivado project must be opened for this step. Copy following TCL Code to the TCL comand console of Vivado:
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#activate extensible platform
set_property platform.extensible true [current_project]
save_bd_design
set_property PFM_NAME [string map {part0 zusys} [string map {trenz.biz trenz} [current_board_part]]] [get_files zusys.bd]
set_property platform.design_intent.embedded {true} [current_project]
set_property platform.design_intent.datacenter {false} [current_project]
set_property platform.design_intent.server_managed {false} [current_project]
set_property platform.design_intent.external_host {false} [current_project]
set_property platform.default_output_type {sd_card} [current_project]
set_property platform.uses_pr {false} [current_project]
save_bd_design
#add clocking wizard
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0
endgroup
#clocking wizard config
set_property -dict [list CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT3_USED {true} CONFIG.CLKOUT4_USED {true} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {400.000} CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {240.000} CONFIG.RESET_TYPE {ACTIVE_LOW} CONFIG.MMCM_CLKOUT1_DIVIDE {6} CONFIG.MMCM_CLKOUT2_DIVIDE {3} CONFIG.MMCM_CLKOUT3_DIVIDE {5} CONFIG.NUM_OUT_CLKS {4} CONFIG.RESET_PORT {resetn} CONFIG.CLKOUT2_JITTER {102.086} CONFIG.CLKOUT2_PHASE_ERROR {87.180} CONFIG.CLKOUT3_JITTER {90.074} CONFIG.CLKOUT3_PHASE_ERROR {87.180} CONFIG.CLKOUT4_JITTER {98.767} CONFIG.CLKOUT4_PHASE_ERROR {87.180}] [get_bd_cells clk_wiz_0]
#connect clocking wizard inputs
connect_bd_net [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
connect_bd_net [get_bd_pins clk_wiz_0/resetn] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
disconnect_bd_net /zynq_ultra_ps_e_0_pl_clk1 [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
disconnect_bd_net /zynq_ultra_ps_e_0_pl_clk1 [get_bd_pins clk_wiz_0/clk_in1]
connect_bd_net [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
connect_bd_net [get_bd_pins clk_wiz_0/clk_out4] [get_bd_pins ps8_0_axi_periph/ACLK]
connect_bd_net [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M/dcm_locked]
save_bd_design
#add reset cores
copy_bd_objs / [get_bd_cells {rst_ps8_0_100M}]
set_property location {3 1279 35} [get_bd_cells clk_wiz_0]
set_property location {4 1564 -146} [get_bd_cells rst_ps8_0_100M1]
copy_bd_objs / [get_bd_cells {rst_ps8_0_100M1}]
set_property location {4 1520 14} [get_bd_cells rst_ps8_0_100M2]
copy_bd_objs / [get_bd_cells {rst_ps8_0_100M2}]
set_property location {4 1498 158} [get_bd_cells rst_ps8_0_100M3]
#connect reset cores
connect_bd_net [get_bd_pins rst_ps8_0_100M1/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_out1]
connect_bd_net [get_bd_pins rst_ps8_0_100M2/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_out2]
connect_bd_net [get_bd_pins rst_ps8_0_100M3/slowest_sync_clk] [get_bd_pins clk_wiz_0/clk_out3]
startgroup
connect_bd_net [get_bd_pins rst_ps8_0_100M2/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins rst_ps8_0_100M1/ext_reset_in]
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] [get_bd_pins rst_ps8_0_100M3/ext_reset_in]
endgroup
startgroup
connect_bd_net [get_bd_pins rst_ps8_0_100M3/dcm_locked] [get_bd_pins clk_wiz_0/locked]
connect_bd_net [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M2/dcm_locked]
connect_bd_net [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M1/dcm_locked]
endgroup
disconnect_bd_net /rst_ps8_0_100M_peripheral_aresetn [get_bd_pins ps8_0_axi_periph/S01_ARESETN]
disconnect_bd_net /rst_ps8_0_100M_peripheral_aresetn [get_bd_pins ps8_0_axi_periph/M00_ARESETN]
disconnect_bd_net /rst_ps8_0_100M_peripheral_aresetn [get_bd_pins ps8_0_axi_periph/S00_ARESETN]
startgroup
connect_bd_net [get_bd_pins ps8_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps8_0_100M/interconnect_aresetn]
connect_bd_net [get_bd_pins rst_ps8_0_100M/interconnect_aresetn] [get_bd_pins ps8_0_axi_periph/S00_ARESETN]
connect_bd_net [get_bd_pins rst_ps8_0_100M/interconnect_aresetn] [get_bd_pins ps8_0_axi_periph/M00_ARESETN]
endgroup
save_bd_design
#add interrupt core
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0
endgroup
#config interrupt core
set_property -dict [list CONFIG.C_KIND_OF_INTR.VALUE_SRC USER] [get_bd_cells axi_intc_0]
set_property -dict [list CONFIG.C_KIND_OF_INTR {0x00000000} CONFIG.C_IRQ_CONNECTION {1}] [get_bd_cells axi_intc_0]
#connect interrupt core
connect_bd_net [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out4]
apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {/clk_wiz_0/clk_out4 (240 MHz)} Clk_slave {/clk_wiz_0/clk_out4 (240 MHz)} Clk_xbar {/clk_wiz_0/clk_out4 (240 MHz)} Master {/zynq_ultra_ps_e_0/M_AXI_HPM0_LPD} Slave {/axi_intc_0/s_axi} ddr_seg {Auto} intc_ip {/ps8_0_axi_periph} master_apm {0}} [get_bd_intf_pins axi_intc_0/s_axi]
save_bd_design
startgroup
set_property -dict [list CONFIG.PSU__USE__IRQ0 {1}] [get_bd_cells zynq_ultra_ps_e_0]
endgroup
save_bd_design
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] [get_bd_pins axi_intc_0/irq]
save_bd_design
disconnect_bd_net /rst_ps8_0_100M_peripheral_aresetn [get_bd_pins ps8_0_axi_periph/M01_ARESETN]
connect_bd_net [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins rst_ps8_0_100M/interconnect_aresetn]
save_bd_design
set_property PFM.CLOCK {clk_out1 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "4" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "4" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "5" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "4" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "5" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "6" is_default "false" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
set_property pfm_name zusys [get_files {zusys.bd}]
set_property PFM.CLOCK {clk_out1 {id "1" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "4" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "5" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "6" is_default "false" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "1" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "4" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "5" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "6" is_default "false" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "1" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "2" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "5" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "6" is_default "false" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "1" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "2" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "6" is_default "false" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "1" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "2" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "4" is_default "false" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
set_property PFM.CLOCK {clk_out1 {id "1" is_default "false" proc_sys_reset "/rst_ps8_0_100M1" status "fixed" freq_hz "100000000"} clk_out2 {id "2" is_default "false" proc_sys_reset "/rst_ps8_0_100M2" status "fixed" freq_hz "200000000"} clk_out3 {id "3" is_default "false" proc_sys_reset "/rst_ps8_0_100M3" status "fixed" freq_hz "400000000"} clk_out4 {id "4" is_default "true" proc_sys_reset "/rst_ps8_0_100M" status "fixed" freq_hz "240000000"}} [get_bd_cells /clk_wiz_0]
save_bd_design
set_property PFM.IRQ {intr { id 0 range 32 }} [get_bd_cells /axi_intc_0]
save_bd_design
set_property PFM.AXI_PORT {S02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
save_bd_design
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "HP2" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "HP2" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "HP3" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
save_bd_design
set_property PFM.AXI_PORT {M_AXI_HPM0_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M_AXI_HPM1_FPD {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S_AXI_HPC0_FPD {memport "S_AXI_HP" sptag "HPC0" memory "" is_range "false"} S_AXI_HPC1_FPD {memport "S_AXI_HP" sptag "HPC1" memory "" is_range "false"} S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "" is_range "false"} S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1" memory "" is_range "false"} S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "HP2" memory "" is_range "false"} S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "HP3" memory "" is_range "false"}} [get_bd_cells /zynq_ultra_ps_e_0]
set_property PFM.AXI_PORT {S03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} S07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {S07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
set_property PFM.AXI_PORT {M02_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} M07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"}} [get_bd_cells /ps8_0_axi_periph]
save_bd_design
#save
save_bd_design
#save project XPR name
global proj_xpr
set proj_xpr [current_project]
append proj_xpr .xpr
#close project
close_project
# reopen project
open_project $proj_xpr
# open block design
open_bd_design [current_project].srcs/sources_1/bd/zusys/zusys.bd
#validate
#validate_bd_design
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This script modifies the Initial platform Block design into the Extensible platform Block design and also defines define Platform Setup configuration.
In Vivado, open the design explorer and Platform description.
The fast track result is identical to the manually performed modifications described in next sections. In Vivado, save block design by clicking on icon “Save Block Design”.
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Continue the design path with Validate Design.
Manual Track
In Vivado project, click in Flow Navigator on Settings. In opened Settings window, select General in Project Settings, select Project is an extensible Vitis platform. Click on OK.
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IP Integrator of project set up as an extensible Vitis platform has an additional Platform Setup window.
Add multiple clocks and processor system reset IPs
In IP Integrator Diagram Window, right click, select Add IP and add Clocking Wizard IP clk_wiz_0. Double-click on the IP to Re-customize IP window. Select Output Clocks panel. Select four clocks with frequency 100, 200, 400 and 240 MHz.
100 MHz clock will serve as low speed clock.
200 MHz and 400 MHz clock will serve as clock for possible AI engine.
240 MHz clock will serve as the default extensible platform clock. By default, Vitis will compile HW IPs with this default clock.
Set reset type from the default Active High to Active Low.
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Clik on OK to close the Re-customize IP window.
Disconnect clock network driven by output pl_clk0 of zynq_ultra_ps_e_0 from pl_clk0 and connect the complete clock network to output clk_out4 of clk_wiz_0. It will be driven by 240 MHz clock.
Connect input resetn of clk_wiz_0 with output pl_resetn0 of zynq_ultra_ps_e_0.
Connect input clk_in1 of clk_wiz_0 with output pl_clk0 of zynq_ultra_ps_e_0.
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Modify lab tools frequency meter for 240 MHz clock.
Open the labtools_fmeter_0 and set the REF Clock in Hz to 240000000.
These modifications are made to support the axi-lite interface of an interrupt controller operating at 240 MHz clock, identical with the default extendable platform clock.
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Add and connect Processor System Reset blocks for each generated clock.
Add four Processor System reser blocks and rename them proc_sys_reset_1, proc_sys_reset_2, proc_sys_reset_3 and proc_sys_reset_4.
Connect input slowest_sync_clk of proc_sys_reset_1 to clk_out1 of clk_wiz_0.
Connect input slowest_sync_clk of proc_sys_reset_2 to clk_out2 of clk_wiz_0.
Connect input slowest_sync_clk of proc_sys_reset_3 to clk_out3 of clk_wiz_0.
Connect input slowest_sync_clk of proc_sys_reset_4 to clk_out4 of clk_wiz_0.
Connect inputs ext_reset_in of proc_sys_reset_1, proc_sys_reset_2 proc_sys_reset_3 and proc_sys_reset_4 tooutput pl_resetn0 of zynq_ultra_ps_e_0.
Connect inputs dcm_locked of proc_sys_reset_1, proc_sys_reset_2 proc_sys_reset_3 and proc_sys_reset_4 tooutput locked of clk_wiz_0.
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Platform Setup - clocks
Open Platform Setup window of IP Integrator to define Clocks. In Settings, select Clock.
In “Enabled” column select all four defined clocks clk_out1, clk_out2, clk_out3, clk_out4 of clk_wiz_0 block.
In “ID” column keep the default Clock ID: 1, 2, 3, 4
In “Is Default” column, select clk_out4 (with ID=4) as the default clock. One and only one clock must be selected as default clock.
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Add, customize and connect the AXI Interrupt Controller
Add AXI Interrupt Controller IP axi_intc_0.
Double-click on axi_intc_0 to re-customize it.
In “Processor Interrupt Type and Connection” section select the “Interrupt Output Connection” from “Bus” to “Single”.
In “Peripherial Interrupt Type” section, change the “Interrupts Types Edge or Level” from AUTO to MANUAL. Change the corresponding value from 0xFFFFFFFF to 0x00000000.
Click on OK to accept these changes.
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| This re-configuration is manually setting all interrupts as level interrupts. With this setting, the PetaLinux automatically creates correct description of the interrupt controller in the device tree. The Vitis extensible flow generates HW IP blocks with level interrupts. |
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| In case of user defined edge interrupts, the corresponding interrupt description will be added in an customised, interrupt controller description section of the user-defined device tree file ~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi For the default extensible TE0821_01_240_pfm platform it is not needed. |
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Connect interrupt controller clock input s_axi_aclk of axi_intc_0 to clock output dlk_out4 of clk_wiz_0. It is the default, 240 MHz clock of the extensible platform.
Connect interrupt controller input s_axi_aresetn of axi_intc_0 to output peripheral_aresetn[0:0] of proc_sys_reset_4 . It is the reset block for default, 240 MHz clock of the extensible platform.
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Use the Run Connection Automation wizard to connect the axi lite interface of interrupt controller axi_intc_0 to zynq_ultra_ps_e_0. It is available in green line in top of the Diagram window.
In Run Connection Automaton window, click OK.
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New AXI interconnect ps_8_axi_periph is created and related connections are generated.
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Vitis extensible design flow will be expanding the AXI interconnect ps_8_axi_periph for interfacing and configuration of registers of generated HW IP blocks with the default extensible platform clock 240 MHz.
Modify the automatically generated reset network of AXI interconnect ps_8_axi_periph IP.
Disconnect input S00_ARESETN of ps_8_axi_periph from the network driven by output peripherial_aresetn[0:0] of proc_sys_reset_4 block.
Connect input S00_ARESETN of ps_8_axi_periph block with output interconnect_aresetn[0:0] of proc_sys_reset_4 block.
Disconnect input M00_ARESETN of ps_8_axi_periph block from the network driven by output peripherial_aresetn[0:0] of proc_sys_reset_4 block.
Connect input M00_ARESETN of ps_8_axi_periph to output interconnect_aresetn[0:0] of proc_sys_reset_4 block.
This modification will make the reset structure of the AXI interconnect ps_8_axi_periph block identical to the future extensions generated by the Vitis extensible design flow.
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Double-click on zynq_ultra_ps_e_0 to re-customize it by enabling of an interrupt input pl_ps_irq0[0:0]. Click OK.
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Connect the interrupt input pl_ps_irq0[0:0] of zynq_ultra_ps_e_0 block with output irq of axi_intc_0 block.
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In Platform Setup, select “Interrupt” and enable intr in the “Enabled” column.
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In Platform Setup, select AXI Port for zynq_ultra_ps_e_0:
Select M_AXI_HPM0_FPD and M_AXI_HPM1_FPD in column “Enabled”.
Select S_AXI_HPC0_FPD and S_AXI_HPC1_FPD in column “Enabled”.
For S_AXI_HPC0_FPD, change S_AXI_HPC to S_AXI_HP in column “Memport”.
For S_AXI_HPC1_FPD, change S_AXI_HPC to S_AXI_HP in column “Memport”.
Select S_AXI_HP0_FPD, S_AXI_HP1_FPD, S_AXI_HP2_FPD, S_AXI_HP3_FPD in column “Enabled”.
Type into the “sptag” column the names for these 6 interfaces so that they can be selected by v++ configuration during linking phase. HPC0, HPC1, HP0, HP1, HP2, HP3
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In “Platform Setup”, select AXI Ports for ps8_0_axi_periph:
Select M01_AXI, M02_AXI, M03_AXI, M04_AXI, M05_AXI, M06_AXI and M07_AXI in column “Enabled”.
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The modifications of the default design for the extensible platform are completed, now.
In Vivado, save block design by clicking on icon “Save Block Design”.
Continue the design path with Validate Design.
Validate Design
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Results of HW creation via Manual Track or Fast Track are identical.
Open diagram by clicking on zusys.bd if not already open.
In Diagram window, validate design by clicking on “Validate Design” icon.
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Received Critical Messages window indicates that input intr[0:0] of axi_intc_0 is not connected. This is expected. The Vitis extensible design flow will connect this input to interrupt outputs from generated HW IPs.
Click OK.
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Known Issue: Sometimes an error in validation process may occur reporting create_pfm function is not known. Workaroud is to close vivado tool and reopen again to correclty load platform export API. |
| Note |
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| You can generate pdf of the block diagram by clicking to any place in diagram window and selecting “Save as PDF File”. Use the offered default file name: ~/work/TE0821_01_240/test_board/vivado/zusys.pdf |
Compile Created HW and Custom SW with Trenz Scripts
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In Vivado Tcl Console, type following script and execute it by Enter. It will take some time to compile HW. HW design and to export the corresponding standard XSA package with included bitstream.
| Code Block | ||
|---|---|---|
| ||
TE::hw_build_design -export_prebuilt |
An archive for standard non-extensible system is created:
~/work/TE0821_01_240/test_board/vivado/test_board_2cg_1e_4gb.xsa
In Vivado Tcl Console, type the following script and execute it by Enter. It will take some time to compile.
| Code Block | ||
|---|---|---|
| ||
TE::sw_run_vitis -all |
After the script controlling SW compilation is finished, the Vitis SDK GUI is opened.
Close the Vitis “Welcome” page.
Compile the two included SW projects.
Standalone custom Vitis platform has been created and compiled.
| Scroll Title | ||
|---|---|---|
| ||
 |
The standalonecustom Vitis platform includes Trenz Electronic custom first stage boot loader in folder zynqmp_fsbl. It includes SW extension specific for the Trenz module initialisation.
This custom zynqmp_fsbl project has been compiled into executable file fsbl.elf. It is located in: ~/work/TE0821_01_240/test_board/prebuilt/software/2cg_4gb/fsbl.elf
This customised first stage boot loader is needed for the Vitis extensible platform.
We have used the standard Trenz scripts to generate it for next use in the extensible platform.
Exit the opened Vitis SDK project.
In Vivado top menu select File->Close Project to close project. Click OK.
In Vivado top menu select File->Exit to close Vivado. Click OK.
The exported Vitis Extensible Hardware platform named test_board_2cg_1e_4gb.xsa can be found in the vivado folder.
Copy Created Custom First Stage Boot Loader
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Up to now,test_board directory has been used for all development.
~/work/TE0821_01_240/test_board
Create new folders:
~/work/TE0821_01_240/test_board_pfm/pfm/boot
~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir
Copy the recently created custom first stage boot loader executable file from
~/work/TE0821_01_240/test_board/prebuilt/software/2cg_1e_4gb/fsbl.elf
to
~/work/TE0821_01_240/test_board_pfm/pfm/boot/fsbl.elf
Building Platform OS and SDK
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Configuration of the Default Trenz Petalinux for the Vitis Extensible Platform
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Change directory to the default Trenz Petalinux folder
~/work/TE0821_01_240/test_board/os/petalinux
Source Vitis and Petalinux scripts to set environment for access to Vitis and PetaLinux tools.
| Code Block | ||
|---|---|---|
| ||
$ source /tools/Xilinx/Vitis/2021.2/settings64.sh $ source ~/petalinux/2021.2/settings.sh |
Configure petalinux with the test_board_2cg_1e_4gb.xsa for the extensible design flow by executing:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-config --get-hw-description=~/work/TE0821_01_240/test_board/vivado |
| Scroll Title | ||
|---|---|---|
| ||
 |
Select Exit->Yes to close this window.
Customize Root File System, Kernel, Device Tree and U-boot
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
In text editor, append definition of 32 interrupts by this text:
| Code Block | ||
|---|---|---|
| ||
&amba { zyxclmm_drm {
compatible = "xlnx,zocl";
status = "okay";
reg = <0x0 0xA0000000 0x0 0x10000>;
interrupt-parent = <&axi_intc_0>;
interrupts = <0 4>, <1 4>, <2 4>, <3 4>,
<4 4>, <5 4>, <6 4>, <7 4>,
<8 4>, <9 4>, <10 4>, <11 4>,
<12 4>, <13 4>, <14 4>, <15 4>,
<16 4>, <17 4>, <18 4>, <19 4>,
<20 4>, <21 4>, <22 4>, <23 4>,
<24 4>, <25 4>, <26 4>, <27 4>,
<28 4>, <29 4>, <30 4>, <31 4>;
};
}; |
to the system-user.dtsi file located in folder:
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/
Download the Vitis-AI 2.0 repository.
In browser, open page:
https://github.com/Xilinx/Vitis-AI/tree/2.0
Clik on green Code button and download Vitis-AI-2.0.zip file.
Unzip Vitis-AI-2.0.zip file to directory ~/Downloads/Vitis-AI.
Copy ~/Downloads/Vitis-AI to ~/vitis_ai_2_0
Delete Vitis-AI-2.0.zip, delete ~/Downloads/Vitis-AI, clean trash.
The directory ~/vitis_ai_2_0 contains the Vitis-AI 2.0 framework, now.
To install the Vitis-AI 2.0 version of shared libraries into rootfs (when generating system image by PetaLinux) we have to copy recepies recipes-vitis-ai to the Petalinux project :
Copy
~/vitis_ai_2_0/tools/Vitis-AI-Recipes/recipes-vitis-ai
to
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/In text editor, append these lines:
| Code Block | ||
|---|---|---|
| ||
CONFIG_xrt CONFIG_xrt-dev CONFIG_zocl CONFIG_opencl-clhpp-dev CONFIG_opencl-headers-dev CONFIG_packagegroup-petalinux-opencv CONFIG_packagegroup-petalinux-opencv-dev CONFIG_dnf CONFIG_e2fsprogs-resize2fs CONFIG_parted CONFIG_resize-part CONFIG_packagegroup-petalinux-vitisai CONFIG_packagegroup-petalinux-self-hosted CONFIG_cmake CONFIG_packagegroup-petalinux-vitisai-dev CONFIG_mesa-megadriver CONFIG_packagegroup-petalinux-x11 CONFIG_packagegroup-petalinux-v4lutils CONFIG_packagegroup-petalinux-matchbox CONFIG_vitis-ai-library CONFIG_vitis-ai-library-dev CONFIG_vitis-ai-library-dbg |
to the user-rootfsconfig file:
~/work/TE0821_01_240/test_board/os/petalinux/project-spec/meta-user/conf/user-rootfsconfig
xrt, xrt-dev and zocl are required for Vitis acceleration flow.
dnf is for package management.
parted, e2fsprogs-resize2fs and resize-part can be used for ext4 partition resize.
Other included packages serve for natively building Vitis AI applications on target board and for running Vitis-AI demo applications with GUI.
The last three packages will enable use of the Vitis-AI 2.0 recepies for installation of the correspoding Vitis-AI 2.0 libraries into rootfs of PetaLinux.
Enable all required packages in Petalinux configuration, from the Ubuntu terminal:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-config -c rootfs |
Select all user packages by typing “y”.All packages will have to have an asterisk.
Still in the RootFS configuration window, go to root directory by select Exit once.
Enable OpenSSH and Disable Dropbear
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Dropbear is the default SSH tool in Vitis Base Embedded Platform. If OpenSSH is used to replace Dropbear, the system could achieve faster data transmission speed over ssh. Created Vitis extensible platform applications may use remote display feature. Using of OpenSSH can improve the display experience.
Go to Image Features.
Disable ssh-server-dropbear and enable ssh-server-openssh and click Exit.
Go to Filesystem Packages->misc->packagegroup-core-ssh-dropbear and disable packagegroup-core-ssh-dropbear.
Go to Filesystem Packages level by Exit twice.
Go to console->network->openssh and enable openssh, openssh-sftp-server, openssh-sshd, openssh-scp.
Go to root level by selection of Exit four times.
Enable Package Management
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Package management feature can allow the board to install and upgrade software packages on the fly.
In rootfs config go to Image Features and enable package-management and debug_tweaks option
Click OK, Exit twice and select Yes to save the changes.
Disable CPU IDLE in Kernel Config
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
CPU IDLE would cause processors get into IDLE state (WFI) when the processor is not in use. When JTAG is connected, the hardware server on host machine talks to the processor regularly. If it talks to a processor in IDLE status, the system will hang because of incomplete AXI transactions.
So, it is recommended to disable the CPU IDLE feature during project development phase.
It can be re-enabled after the design has completed to save power in final products.
Launch kernel config:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-config -c kernel |
Ensure the following items are TURNED OFF by entering 'n' in the [ ] menu selection:
CPU Power Management->CPU Idle->CPU idle PM support
CPU Power Management->CPU Frequency scaling->CPU Frequency scaling
Exit and Yes to Save changes.
Add EXT4 rootfs Support
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
Let PetaLinux generate EXT4 rootfs. In terminal, execute:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-config |
Go to Image Packaging Configuration.
Enter into Root File System Type
Select Root File System Type EXT4
Change the “Device node” of SD device from the default value
/dev/mmcblk0p2
to new value required for the TE0821 modules on TE0706-03 carrier:
/dev/mmcblk1p2
Exit and Yes to save changes.
Let Linux Use EXT4 rootfs During Boot
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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The setting of which rootfs to use during boot is controlled by bootargs. We would change bootargs settings to allow Linux to boot from EXT4 partition.
In terminal, execute:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-config |
Change DTG settings->Kernel Bootargs->generate boot args automatically to NO.
Update User Set Kernel Bootargs to:
earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk1p2 rw rootwait cma=512M
Click OK, Exit three times and Save.
Build PetaLinux Image
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In terminal, build the PetaLinux project by executing:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-build |
The PetaLinux image files will be generated in the directory:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux
Generation of PetaLinux takes some time and requires Ethernet connection and sufficient free disk space.
Create Petalinux SDK
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The SDK is used by Vitis tool to cross compile applications for newly created platfom.
In terminal, execute:
| Code Block | ||
|---|---|---|
| ||
$ petalinux-build --sdk |
The generated sysroot package sdk.sh will be located in directory
~/work/TE0821_01_240/test_board/os/petalinux/images/linux
Generation of SDK package takes some time and requires sufficient free disk space.
Time needed for these two steps depends also on number of allocated processor cores.
Copy Files for Extensible Platform
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Copy these four files:
| Scroll Title | ||||||
|---|---|---|---|---|---|---|
| ||||||
|
Rename the copied file u-boot-dtb.elf to u-boot.elf
The directory
~/work/TE0821_01_240/test_board_pfm/pfm/boot
contains these five files:
- bl31.elf
- fsbl.elf
- pmufw.elf
- system.dtb
- u-boot.elf
Copy files:
| Scroll Title | ||||||
|---|---|---|---|---|---|---|
| ||||||
|
Copy file:
| Scroll Title | ||||||
|---|---|---|---|---|---|---|
| ||||||
|
| Note | |||||
|---|---|---|---|---|---|
init.sh is an place-holder for user defined bash code to be executed after the boot:
|
Create Extensible Platform zip File
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
Create new directory tree:
~/work/TE0821_01_240_move/test_board/os/petalinux/images
~/work/TE0821_01_240_move/test_board/Vivado
~/work/TE0821_01_240_move/test_board_pfm/pfm/boot ~/work/TE0821_01_240_move/test_board_pfm/pfm/sd_dir
Copy all files from the directory:
| Scroll Title | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||
|
Zip the directory
~/work/TE0821_01_240_move
into ZIP archive:
~/work/TE0821_01_240_move.zip
The archive TE0821_01_240_move.zip can be used to create extensible platform on the same or on an another PC with installed Ubuntu 20.04 and Vitis tools, with or without installed Petalinux. The archive includes all needed components, including the Xilinx xrt library and the script sdk.sh serving for generation of the sysroot .
The zip archive has size approximately 5.3 GB.
Move the TE0821_01_240_move.zip file to an PC disk drive.
Delete:
~/work/TE0821_01_240_move
~/work/TE0821_01_240_move.zip
Clean the Ubuntu Trash.
Generation of SYSROOT
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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This part of development can be direct continuation of the previous Petalinux configuration and compilation steps.
| Note |
|---|
| Alternatively, it is also possible to implement all next steps on an Ubuntu 20.04 without installed PetaLinux Only the Ubuntu 20.04 and Vitis/Vivado installation is needed. All required files created in the PetaLinux for the specific module (24) are present in the archive: TE0821_01_240_move.zip In this case, unzip the archive to the directory: ~/work/TE0821_01_240_move and copy all content of directories to ~/work/TE0821_01_240 Delete the TE0821_01_240_move.zip file and the ~/work/TE0821_01_240_move directory to save filesystem space. |
In Ubuntu terminal, change the working directory to:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux
In Ubuntu terminal, execute script enabling access to Vitis 2021 tools.
Execution of script serving for setting up PetaLinux environment is not necessary:
| Code Block | ||
|---|---|---|
| ||
$ source /tools/Xilinx/Vitis/2021.2/settings64.sh |
In Ubuntu terminal, execute script
| Code Block | ||
|---|---|---|
| ||
$ ./sdk.sh -d ~/work/TE0821_01_240/test_board_pfm |
SYSROOT directories and files for PC and for Zynq Ultrascale+ will be created in:
~/work/TE0821_01_240/test_board_pfm/sysroots/x86_64-petalinux-linux
~/work/TE0821_01_240/test_board_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
Once created, do not move these sysroot directories (due to some internally created paths).
Generation of Extensible Platform for Vitis
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In Ubuntu terminal, change the working directory to:
~/work/TE0821_01_240/test_board_pfm
Start the Vitis tool by executing
| Code Block | ||
|---|---|---|
| ||
$ vitis & |
In Vitis “Launcher”, set the workspace for the extensible platform compilation:
~/work/TE0821_01_240/test_board_pfm
Click on “Launch” to launch Vitis
Close Welcome page.
In Vitis, select in the main menu: File -> New -> Platform Project
Type name of the extensible platform: TE0821_01_240_pfm. Click Next.
| Scroll Title | ||
|---|---|---|
| ||
 |
Choose for hardware specification for the platform file:
~/work/TE0821_01_240/test_board/vivado/test_board_2cg_1e_4gb.xsa
In “Software specification” select: linux
In “Boot Components” unselect Generate boot components
(these components have been already generated by Vivado and PetaLinux design flow)
New window TE0821_01_240_pfm is opened.
Click on linux on psu_cortex53 to open window Domain: linux_domain
In “Description”: write xrt
In “Bif File” find and select the pre-defied option: Generate Bif
In “Boot Components Directory” select:
~/work/TE0821_01_240/test_board_pfm/pfm/boot
In “FAT32 Partition Directory” select:
~/work/TE0821_01_240/test_board_pfm/pfm/sd_dir
| Scroll Title | ||
|---|---|---|
| ||
 |
In Vitis IDE “Explorer” section, click on TE0821_01_240_pfm to highlight it.
Right-click on the highlighted TE0821_01_240_pfm and select build project in the open submenu. Platform is compiled in few seconds.
Close the Vitis tool by selection: File -> Exit.
| Scroll Title | ||
|---|---|---|
| ||
 |
Vitis extensible platform TE0821_01_240_pfm has been created in the directory:
~/work/TE0821_01_240/test_board_pfm/TE0821_01_240_pfm/export/TE0821_01_240_pfm
Platform Usage
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Test 1: Read Platform Info
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
With Vitis environment setup, platforminfo tool can report XPFM platform information.
| Code Block | ||
|---|---|---|
| ||
platforminfo ~/work/TE0821_01_240/test_board_pfm/TE0821_01_240_pfm/export/TE0821_01_240_pfm/TE0821_01_240_pfm.xpfm |
| Code Block | ||||
|---|---|---|---|---|
| ||||
==========================
Basic Platform Information
==========================
Platform: te0821_01_240_pfm
File: /home/devel/work/te0821_01_240/test_board_pfm/te0821_01_240_pfm/export/te0821_01_240_pfm/te0821_01_240_pfm.xpfm
Description:
te0821_01_240_pfm
=====================================
Hardware Platform (Shell) Information
=====================================
Vendor: vendor
Board: zusys
Name: zusys
Version: 1.0
Generated Version: 2021.2.1
Hardware: 1
Software Emulation: 1
Hardware Emulation: 1
Hardware Emulation Platform: 0
FPGA Family: zynquplus
FPGA Device: xczu2cg
Board Vendor: trenz.biz
Board Name: trenz.biz:te0821_2cg_1e:3.0
Board Part: xczu2cg-sfvc784-1-e
=================
Clock Information
=================
Default Clock Index: 4
Clock Index: 1
Frequency: 100.000000
Clock Index: 2
Frequency: 200.000000
Clock Index: 3
Frequency: 400.000000
Clock Index: 4
Frequency: 240.000000
==================
Memory Information
==================
Bus SP Tag: HP0
Bus SP Tag: HP1
Bus SP Tag: HP2
Bus SP Tag: HP3
Bus SP Tag: HPC0
Bus SP Tag: HPC1
=============================
Software Platform Information
=============================
Number of Runtimes: 1
Default System Configuration: te0821_01_240_pfm
System Configurations:
System Config Name: te0821_01_240_pfm
System Config Description: te0821_01_240_pfm
System Config Default Processor Group: linux_domain
System Config Default Boot Image: standard
System Config Is QEMU Supported: 1
System Config Processor Groups:
Processor Group Name: linux on psu_cortexa53
Processor Group CPU Type: cortex-a53
Processor Group OS Name: linux
System Config Boot Images:
Boot Image Name: standard
Boot Image Type:
Boot Image BIF: te0821_01_240_pfm/boot/linux.bif
Boot Image Data: te0821_01_240_pfm/linux_domain/image
Boot Image Boot Mode: sd
Boot Image RootFileSystem:
Boot Image Mount Path: /mnt
Boot Image Read Me: te0821_01_240_pfm/boot/generic.readme
Boot Image QEMU Args: te0821_01_240_pfm/qemu/pmu_args.txt:te0821_01_240_pfm/qemu/qemu_args.txt
Boot Image QEMU Boot:
Boot Image QEMU Dev Tree:
Supported Runtimes:
Runtime: OpenCL
|
Test 2: Run Vector Addition Example
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
Create new directorytest_board_test_vadd to test Vitis extendable flow example “vector addition”
~/work/TE0821_01_240/test_board_test_vadd
Current directory structure:
~/work/TE0821_01_240/test_board
~/work/TE0821_01_240/test_board_pfm
~/work/TE0821_01_240/test_board_test_vadd
Change working directory:
| Code Block | ||
|---|---|---|
| ||
$cd ~/work/TE0821_01_240/test_board_test_vadd |
In Ubuntu terminal, start Vitis by:
| Code Block | ||
|---|---|---|
| ||
$ vitis & |
In Vitis IDE Launcher, select your working directory
~/work/TE0821_01_240/test_board_test_vadd
Click on Launch to launch Vitis.
Select File -> New -> Application project. Click Next.
Skip welcome page if shown.
Click on “+ Add” icon and select the custom extensible platform TE0821_01_240_pfm[custom] in the directory:
~/work/TE0821_01_240/test_board_pfm/TE0821_01_240_pfm/export/TE0821_01_240_pfm
We can see available PL clocks and frequencies.
| Note |
|---|
| PL4 with 240 MHz clock is has been set as default in the platform creation process. |
| Scroll Title | ||
|---|---|---|
| ||
 |
Click Next.
In “Application Project Details” window type into Application project name: test_vadd
Click Next.
In “Domain window” type (or select by browse):
“Sysroot path”:
~/work/TE0821_01_240/test_board_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
“Root FS”:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/rootfs.ext4
“Kernel Image”:
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/Image
Click Next.
In “Templates window”, if not done before, update “Vitis IDE Examples” and “Vitis IDE Libraries”.
Select Host Examples
In “Find”, type: “vector add” to search for the “Vector Addition” example.
Select: “Vector Addition”
Click Finish
New project template is created.
In test_vadd window menu “Active build configuration” switch from “SW Emulation” to “Hardware”.
In “Explorer” section of Vitis IDE, click on: test_vadd_system[TE0821_01_240_pfm] to select it.
Right Click on: test_vadd_system[TE0821_01_240_pfm] and select in the opened sub-menu:
Build project
Vitis will compile:
In test_vadd_kernels subproject, compile the krnl_vadd from C++ SW to HDL HW IP source code
In test_vadd_system_hw_link subproject, compile the krnl_vadd HDL together with TE0821_01_240_pfm into new, extended HW design with new accelerated (krnl_vadd) will run on the default 240 MHz clock. This step can take some time.
In test_vadd subproject, compile the vadd.cpp application example.
| Scroll Title | ||
|---|---|---|
| ||
 |
Run Compiled Example Application
| Scroll Ignore | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||
The sd_card.img file is output of the compilation and packing by Vitis. It is located in directory:
~/work/TE0821_01_240/test_board_test_vadd/test_vadd_system/Hardware/package/sd_card.img
Write the sd card image from the sd_card.img file to SD card.
| Note |
|---|
| In Windows Pro 10 (or Windows 11 Pro) PC, inst all program Win32DiskImager for this task. Win32 Disk Imager can write raw disk image to removable devices. https://win32diskimager.org/ |
Insert the SD card to the TE0706-03 carrier board.
Connect PC USB terminal (115200 bps) card to the TE0706-03 carrier board.
Connect USB Keyboard and USB Mouse to the TE0706-03 carrier board.
Connect Ethernet cable to the TE0706-03 carrier board.
Power on the TE0706-03 carrier board.
In PC, find the assigned serial line COM port number for the USB terminal. In case of Win 10 use device manager.
In PC, open serial line terminal with the assigned COM port number. Speed 115200 bps.
Connect Monitor to the Display Port connector of the TE0706-03 carrier board.
On TE0706-03, press button S1 to start the system (press the button for cca. 1 sec. ).
(FMC fan starts to rotate, USB terminal starts to display booting information)
Display Port Monitor indicates text “Please wait: Booting…” (white text, black background).
X11 screen opens on Display port.
Mouse and keyboard connected to the TE0706-03 carrier board can be used.
Click on “Terminal” icon (A Unicode capable rxvt)
Terminal opens as an X11 graphic window.
In terminal, use keyboard connected to the TE0706-03 carrier board and type:
| Code Block | ||
|---|---|---|
| ||
sh-5.0# cd /media/sd-mmcblk1p1/ sh-5.0# ./test_vadd krnl_vadd.xclbin |
The application test_vadd should run with this output:
| Code Block | ||
|---|---|---|
| ||
sh-5.0# cd /media/sd-mmcblk1p1/ sh-5.0# ./test_vadd krnl_vadd.xclbin INFO: Reading krnl_vadd.xclbin Loading: 'krnl_vadd.xclbin' Trying to program device[0]: edge Device[0]: program successful! TEST PASSED sh-5.0# |
The Vitis application has been compiled to HW and evaluated on custom system
with extensible custom TE0821_01_240_pfm platform.
Close the rxvt terminal emulator by click ”x” icon (in the upper right corner) or by typing:
| Code Block | ||
|---|---|---|
| ||
# exit |
In X11, click on ”Shutdown” icon to close down safely.
System is halted. Messages relate to halt of the system can be seen on the USB terminal).
The SD card can be safely removed from the TE0706-03 carrier board, now.
The TE0706-03 carrier board can be disconnected from power.
| Note | |||||
|---|---|---|---|---|---|
The TE0706-03 carrier with TE0821-01-2AE31KA module No. 1 with device xczu2cg-sfvc784-1-e and 4GB memory is running the PetaLinux OS and drives simple version of an X11 GUI on a PC with Ubuntu 20.04 on virtual machine. Application test_vadd is executed in remote X11 terminal. |
| Code Block | ||||||
|---|---|---|---|---|---|---|
| ||||||
--------------------------------------------------------------------------------
TE0821 TE_XFsbl_HookPsuInit_Custom
Configure PLL: SI5338-B
Si5338 Init Registers Write.
Si5338 Init Complete
PLL Status Register 218:0x8
USB Reset Complete
ETH Reset Complete
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Xilinx Zynq MP First Stage Boot Loader (TE modified)
Release 2021.2 Dec 1 2022 - 18:37:26
Device Name: XCZU2CG
--------------------------------------------------------------------------------
TE0821 TE_XFsbl_BoardInit_Custom
--------------------------------------------------------------------------------
NOTICE: BL31: v2.4(release):xlnx_rebase_v2.4_2021.1_update1-23-g9188496b9
NOTICE: BL31: Built : 07:41:24, Oct 13 2021
U-Boot 2021.01 (Oct 12 2021 - 09:28:42 +0000)
CPU: ZynqMP
Silicon: v3
Board: Xilinx ZynqMP
DRAM: 4 GiB
PMUFW: v1.1
EL Level: EL2
Chip ID: zu2cg
NAND: 0 MiB
MMC: mmc@ff160000: 0, mmc@ff170000: 1
Loading Environment from FAT... Unable to use mmc 0:0... In: serial
Out: serial
Err: serial
Bootmode: SD_MODE1
Reset reason: EXTERNAL
Net:
ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 1, interface rgmii-id
Warning: ethernet@ff0e0000 (eth0) using random MAC address - da:63:af:98:9d:a5
eth0: ethernet@ff0e0000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1...
Found U-Boot script /boot.scr
2710 bytes read in 16 ms (165 KiB/s)
## Executing script at 20000000
Trying to load boot images from mmc1
21451264 bytes read in 1990 ms (10.3 MiB/s)
40869 bytes read in 19 ms (2.1 MiB/s)
## Flattened Device Tree blob at 00100000
Booting using the fdt blob at 0x100000
Loading Device Tree to 000000007dd04000, end 000000007dd10fa4 ... OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.10.0-xilinx-v2021.2 (oe-user@oe-host) (aarch64-xilinx-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.1) #1 SMP Tue Oct 12 09:30:57 UTC 2021
[ 0.000000] Machine model: xlnx,zynqmp
[ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
[ 0.000000] printk: bootconsole [cdns0] enabled
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 512 MiB at 0x000000005dc00000
[ 0.000000] Zone ranges:
[ 0.000000] DMA32 [mem 0x0000000000000000-0x00000000ffffffff]
[ 0.000000] Normal [mem 0x0000000100000000-0x000000087fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x000000007fefffff]
[ 0.000000] node 0: [mem 0x0000000800000000-0x000000087fffffff]
[ 0.000000] Zeroed struct page in unavailable ranges: 256 pages
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff]
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.2
[ 0.000000] percpu: Embedded 22 pages/cpu s49624 r8192 d32296 u90112
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: detected: ARM erratum 845719
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031940
[ 0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk1p2 rw rootwait cma=512M
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] software IO TLB: mapped [mem 0x0000000059c00000-0x000000005dc00000] (64MB)
[ 0.000000] Memory: 3501236K/4193280K available (13888K kernel code, 980K rwdata, 3904K rodata, 2048K init, 588K bss, 167756K reserved, 524288K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] irq-xilinx: /amba_pl@0/interrupt-controller@80010000: num_irq=32, sw_irq=0, edge=0x0
[ 0.000000] random: get_random_bytes called from start_kernel+0x31c/0x524 with crng_init=0
[ 0.000000] arch_timer: cp15 timer(s) running at 33.33MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x7b00c47c0, max_idle_ns: 440795202120 ns
[ 0.000003] sched_clock: 56 bits at 33MHz, resolution 30ns, wraps every 2199023255541ns
[ 0.008249] Console: colour dummy device 80x25
[ 0.012393] Calibrating delay loop (skipped), value calculated using timer frequency.. 66.66 BogoMIPS (lpj=133333)
[ 0.022668] pid_max: default: 32768 minimum: 301
[ 0.027381] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.034617] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.043409] rcu: Hierarchical SRCU implementation.
[ 0.047375] EFI services will not be available.
[ 0.051742] smp: Bringing up secondary CPUs ...
[ 0.056514] Detected VIPT I-cache on CPU1
[ 0.056551] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.056613] smp: Brought up 1 node, 2 CPUs
[ 0.070674] SMP: Total of 2 processors activated.
[ 0.075347] CPU features: detected: 32-bit EL0 Support
[ 0.080451] CPU features: detected: CRC32 instructions
[ 0.085584] CPU: All CPU(s) started at EL2
[ 0.089627] alternatives: patching kernel code
[ 0.095091] devtmpfs: initialized
[ 0.101492] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.107015] futex hash table entries: 512 (order: 3, 32768 bytes, linear)
[ 0.126755] pinctrl core: initialized pinctrl subsystem
[ 0.127173] DMI not present or invalid.
[ 0.130347] NET: Registered protocol family 16
[ 0.135600] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[ 0.141667] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[ 0.149470] audit: initializing netlink subsys (disabled)
[ 0.154923] audit: type=2000 audit(0.108:1): state=initialized audit_enabled=0 res=1
[ 0.155288] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.169277] ASID allocator initialised with 65536 entries
[ 0.174715] Serial: AMBA PL011 UART driver
[ 0.199436] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[ 0.200490] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[ 0.207164] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.213821] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[ 1.265729] cryptd: max_cpu_qlen set to 1000
[ 1.289971] DRBG: Continuing without Jitter RNG
[ 1.369325] raid6: neonx8 gen() 2139 MB/s
[ 1.437379] raid6: neonx8 xor() 1596 MB/s
[ 1.505449] raid6: neonx4 gen() 2185 MB/s
[ 1.573506] raid6: neonx4 xor() 1566 MB/s
[ 1.641575] raid6: neonx2 gen() 2076 MB/s
[ 1.709630] raid6: neonx2 xor() 1435 MB/s
[ 1.777716] raid6: neonx1 gen() 1770 MB/s
[ 1.845767] raid6: neonx1 xor() 1219 MB/s
[ 1.913840] raid6: int64x8 gen() 1437 MB/s
[ 1.981897] raid6: int64x8 xor() 771 MB/s
[ 2.049966] raid6: int64x4 gen() 1601 MB/s
[ 2.118032] raid6: int64x4 xor() 819 MB/s
[ 2.186100] raid6: int64x2 gen() 1397 MB/s
[ 2.254174] raid6: int64x2 xor() 750 MB/s
[ 2.322250] raid6: int64x1 gen() 1031 MB/s
[ 2.390300] raid6: int64x1 xor() 517 MB/s
[ 2.390337] raid6: using algorithm neonx4 gen() 2185 MB/s
[ 2.394298] raid6: .... xor() 1566 MB/s, rmw enabled
[ 2.399228] raid6: using neon recovery algorithm
[ 2.404234] iommu: Default domain type: Translated
[ 2.408869] SCSI subsystem initialized
[ 2.412511] usbcore: registered new interface driver usbfs
[ 2.417860] usbcore: registered new interface driver hub
[ 2.423127] usbcore: registered new device driver usb
[ 2.428172] mc: Linux media interface: v0.10
[ 2.432374] videodev: Linux video capture interface: v2.00
[ 2.437846] EDAC MC: Ver: 3.0.0
[ 2.441291] zynqmp-ipi-mbox mailbox@ff990400: Registered ZynqMP IPI mbox with TX/RX channels.
[ 2.449577] FPGA manager framework
[ 2.452882] Advanced Linux Sound Architecture Driver Initialized.
[ 2.459113] Bluetooth: Core ver 2.22
[ 2.462385] NET: Registered protocol family 31
[ 2.466789] Bluetooth: HCI device and connection manager initialized
[ 2.473103] Bluetooth: HCI socket layer initialized
[ 2.477945] Bluetooth: L2CAP socket layer initialized
[ 2.482968] Bluetooth: SCO socket layer initialized
[ 2.488057] clocksource: Switched to clocksource arch_sys_counter
[ 2.493987] VFS: Disk quotas dquot_6.6.0
[ 2.497794] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 2.508656] NET: Registered protocol family 2
[ 2.509245] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[ 2.517434] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[ 2.525461] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear)
[ 2.532915] TCP: Hash tables configured (established 32768 bind 32768)
[ 2.539077] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[ 2.545747] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[ 2.552913] NET: Registered protocol family 1
[ 2.557388] RPC: Registered named UNIX socket transport module.
[ 2.562982] RPC: Registered udp transport module.
[ 2.567647] RPC: Registered tcp transport module.
[ 2.572316] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.579303] PCI: CLS 0 bytes, default 64
[ 2.608680] Initialise system trusted keyrings
[ 2.608812] workingset: timestamp_bits=46 max_order=20 bucket_order=0
[ 2.614651] NFS: Registering the id_resolver key type
[ 2.618931] Key type id_resolver registered
[ 2.623082] Key type id_legacy registered
[ 2.627064] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 2.633719] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc.
[ 2.677014] NET: Registered protocol family 38
[ 2.677057] xor: measuring software checksum speed
[ 2.684757] 8regs : 2363 MB/sec
[ 2.688418] 32regs : 2799 MB/sec
[ 2.693358] arm64_neon : 2380 MB/sec
[ 2.693548] xor: using function: 32regs (2799 MB/sec)
[ 2.698574] Key type asymmetric registered
[ 2.702636] Asymmetric key parser 'x509' registered
[ 2.707500] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 2.714835] io scheduler mq-deadline registered
[ 2.719330] io scheduler kyber registered
[ 2.725060] ps_pcie_dma init()
[ 2.750952] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.752660] Serial: AMBA driver
[ 2.756657] cacheinfo: Unable to detect cache hierarchy for CPU 0
[ 2.765361] brd: module loaded
[ 2.769333] loop: module loaded
[ 2.770019] mtdoops: mtd device (mtddev=name/number) must be supplied
[ 2.774758] libphy: Fixed MDIO Bus: probed
[ 2.778699] tun: Universal TUN/TAP device driver, 1.6
[ 2.782539] CAN device driver interface
[ 2.786894] usbcore: registered new interface driver asix
[ 2.791666] usbcore: registered new interface driver ax88179_178a
[ 2.797703] usbcore: registered new interface driver cdc_ether
[ 2.803503] usbcore: registered new interface driver net1080
[ 2.809119] usbcore: registered new interface driver cdc_subset
[ 2.815002] usbcore: registered new interface driver zaurus
[ 2.820550] usbcore: registered new interface driver cdc_ncm
[ 2.826935] usbcore: registered new interface driver uas
[ 2.831454] usbcore: registered new interface driver usb-storage
[ 2.837982] rtc_zynqmp ffa60000.rtc: registered as rtc0
[ 2.842598] rtc_zynqmp ffa60000.rtc: setting system clock to 2018-03-09T12:36:32 UTC (1520598992)
[ 2.851448] i2c /dev entries driver
[ 2.856264] usbcore: registered new interface driver uvcvideo
[ 2.860569] USB Video Class driver (1.1.1)
[ 2.865091] Bluetooth: HCI UART driver ver 2.3
[ 2.869053] Bluetooth: HCI UART protocol H4 registered
[ 2.874151] Bluetooth: HCI UART protocol BCSP registered
[ 2.879441] Bluetooth: HCI UART protocol LL registered
[ 2.884530] Bluetooth: HCI UART protocol ATH3K registered
[ 2.889903] Bluetooth: HCI UART protocol Three-wire (H5) registered
[ 2.896150] Bluetooth: HCI UART protocol Intel registered
[ 2.901498] Bluetooth: HCI UART protocol QCA registered
[ 2.906695] usbcore: registered new interface driver bcm203x
[ 2.912320] usbcore: registered new interface driver bpa10x
[ 2.917854] usbcore: registered new interface driver bfusb
[ 2.923304] usbcore: registered new interface driver btusb
[ 2.928763] usbcore: registered new interface driver ath3k
[ 2.934255] EDAC MC: ECC not enabled
[ 2.937840] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[ 2.946789] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[ 2.958992] sdhci: Secure Digital Host Controller Interface driver
[ 2.964888] sdhci: Copyright(c) Pierre Ossman
[ 2.969212] sdhci-pltfm: SDHCI platform and OF driver helper
[ 2.975100] ledtrig-cpu: registered to indicate activity on CPUs
[ 2.980814] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[ 2.987238] zynqmp_firmware_probe Platform Management API v1.1
[ 2.993003] zynqmp_firmware_probe Trustzone version v1.0
[ 3.045859] securefw securefw: securefw probed
[ 3.046116] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[ 3.050355] zynqmp_aes firmware:zynqmp-firmware:zynqmp-aes: AES Successfully Registered
[ 3.058422] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[ 3.064576] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[ 3.070084] usbcore: registered new interface driver usbhid
[ 3.075463] usbhid: USB HID core driver
[ 3.081911] ARM CCI_400_r1 PMU driver probed
[ 3.082349] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[ 3.090315] usbcore: registered new interface driver snd-usb-audio
[ 3.096803] pktgen: Packet Generator for packet performance testing. Version: 2.75
[ 3.104086] Initializing XFRM netlink socket
[ 3.107868] NET: Registered protocol family 10
[ 3.112610] Segment Routing with IPv6
[ 3.116011] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[ 3.122075] NET: Registered protocol family 17
[ 3.126162] NET: Registered protocol family 15
[ 3.130576] can: controller area network core
[ 3.134908] NET: Registered protocol family 29
[ 3.139303] can: raw protocol
[ 3.142239] can: broadcast manager protocol
[ 3.146394] can: netlink gateway - max_hops=1
[ 3.150789] Bluetooth: RFCOMM TTY layer initialized
[ 3.155570] Bluetooth: RFCOMM socket layer initialized
[ 3.160679] Bluetooth: RFCOMM ver 1.11
[ 3.164390] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 3.169660] Bluetooth: BNEP filters: protocol multicast
[ 3.174850] Bluetooth: BNEP socket layer initialized
[ 3.179780] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[ 3.185664] Bluetooth: HIDP socket layer initialized
[ 3.190701] 9pnet: Installing 9P2000 support
[ 3.194847] Key type dns_resolver registered
[ 3.199184] registered taskstats version 1
[ 3.203136] Loading compiled-in X.509 certificates
[ 3.208886] Btrfs loaded, crc32c=crc32c-generic
[ 3.220993] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 48, base_baud = 6249999) is a xuartps
[ 3.230013] printk: console [ttyPS0] enabled
[ 3.230013] printk: console [ttyPS0] enabled
[ 3.234312] printk: bootconsole [cdns0] disabled
[ 3.234312] printk: bootconsole [cdns0] disabled
[ 3.243675] of-fpga-region fpga-full: FPGA Region probed
[ 3.253808] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[ 3.260993] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[ 3.268174] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[ 3.275346] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[ 3.282519] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[ 3.289686] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[ 3.296852] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[ 3.304028] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[ 3.311262] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[ 3.318445] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[ 3.325611] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[ 3.332788] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[ 3.339959] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[ 3.347139] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[ 3.354306] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[ 3.361478] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[ 3.369352] spi-nor spi0.0: trying to lock already unlocked area
[ 3.375357] spi-nor spi0.0: mt25qu512a (131072 Kbytes)
[ 3.380519] 4 fixed-partitions partitions found on MTD device spi0.0
[ 3.386862] Creating 4 MTD partitions on "spi0.0":
[ 3.391645] 0x000000000000-0x000002000000 : "boot"
[ 3.397153] 0x000002000000-0x000002040000 : "bootenv"
[ 3.402840] 0x000002040000-0x000004040000 : "kernel"
[ 3.408442] 0x000004040000-0x0000040c0000 : "bootscr"
[ 3.414561] macb ff0e0000.ethernet: Not enabling partial store and forward
[ 3.421996] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[ 3.428569] zynqmp_pll_disable() clock disable failed for dpll_int, ret = -13
[ 3.435780] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[ 3.442324] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[ 3.448858] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[ 3.472876] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[ 3.478377] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[ 3.486125] xhci-hcd xhci-hcd.1.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000000002010010
[ 3.495529] xhci-hcd xhci-hcd.1.auto: irq 84, io mem 0xfe200000
[ 3.501646] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.509903] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.517112] usb usb1: Product: xHCI Host Controller
[ 3.521983] usb usb1: Manufacturer: Linux 5.10.0-xilinx-v2021.2 xhci-hcd
[ 3.528675] usb usb1: SerialNumber: xhci-hcd.1.auto
[ 3.533830] hub 1-0:1.0: USB hub found
[ 3.537596] hub 1-0:1.0: 1 port detected
[ 3.541703] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[ 3.547189] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[ 3.554846] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[ 3.561403] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 3.569557] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
[ 3.577818] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.585036] usb usb2: Product: xHCI Host Controller
[ 3.589905] usb usb2: Manufacturer: Linux 5.10.0-xilinx-v2021.2 xhci-hcd
[ 3.596600] usb usb2: SerialNumber: xhci-hcd.1.auto
[ 3.601721] hub 2-0:1.0: USB hub found
[ 3.605487] hub 2-0:1.0: 1 port detected
[ 3.610454] at24 0-0050: supply vcc not found, using dummy regulator
[ 3.617093] at24 0-0050: 256 byte 24aa025 EEPROM, writable, 1 bytes/write
[ 3.623912] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 39
[ 3.630198] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[ 3.637689] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s
[ 3.645590] macb ff0e0000.ethernet: Not enabling partial store and forward
[ 3.656137] libphy: MACB_mii_bus: probed
[ 3.661031] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 37 (80:1f:12:f2:b8:ff)
[ 3.673484] of_cfs_init
[ 3.675936] of_cfs_init: OK
[ 3.678851] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 3.688078] mmc0: SDHCI controller on ff160000.mmc [ff160000.mmc] using ADMA 64-bit
[ 3.695839] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[ 3.737216] mmc1: Problem switching card into high-speed mode!
[ 3.743622] mmc1: new SDHC card at address 0001
[ 3.748517] mmcblk1: mmc1:0001 SD16G 14.5 GiB
[ 3.754630] mmcblk1: p1 p2
[ 3.778502] mmc0: new HS200 MMC card at address 0001
[ 3.783792] mmcblk0: mmc0:0001 IS064G 58.3 GiB
[ 3.788506] mmcblk0boot0: mmc0:0001 IS064G partition 1 4.00 MiB
[ 3.794617] mmcblk0boot1: mmc0:0001 IS064G partition 2 4.00 MiB
[ 3.800637] mmcblk0rpmb: mmc0:0001 IS064G partition 3 4.00 MiB, chardev (245:0)
[ 3.815562] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 3.822099] clk: Not disabling unused clocks
[ 3.826560] ALSA device list:
[ 3.829526] No soundcards found.
[ 3.833204] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 3.841812] cfg80211: failed to load regulatory.db
[ 3.873260] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[ 3.881371] VFS: Mounted root (ext4 filesystem) on device 179:2.
[ 3.888644] devtmpfs: mounted
[ 3.892238] Freeing unused kernel memory: 2048K
[ 3.896835] Run /sbin/init as init process
INIT: version 2.97 booting
[ 4.206280] random: fast init done
Starting udev
[ 5.074108] udevd[243]: starting version 3.2.9
[ 5.120318] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.127894] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.134360] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.229173] udevd[244]: starting eudev-3.2.9
[ 5.452520] zocl: loading out-of-tree module taints kernel.
[ 5.460748] [drm] Probing for xlnx,zocl
[ 5.464758] zocl-drm a0000000.zyxclmm_drm: IRQ index 32 not found
[ 5.470941] [drm] FPGA programming device pcap founded.
[ 5.476161] [drm] PR Isolation addr 0x0
[ 5.476835] [drm] Initialized zocl 0.0.0 00000 for a0000000.zyxclmm_drm on minor 0
[ 5.488353] [drm] Probing for xlnx,zocl
[ 5.492513] zocl-drm amba_pl@0:zyxclmm_drm: IRQ index 32 not found
[ 5.498778] [drm] FPGA programming device pcap founded.
[ 5.503994] [drm] PR Isolation addr 0x0
[ 5.504286] [drm] Initialized zocl 0.0.0 00000 for amba_pl@0:zyxclmm_drm on minor 1
[ 6.817603] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null)
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc: started, v1.32.0
udhcpc: sending discover
udhcpc: sending discover
udhcpc: sending discover
udhcpc: sending select for 192.168.13.45
udhcpc: lease of 192.168.13.45 obtained, lease time 3600
/etc/udhcpc.d/50default: Adding DNS 147.231.12.1
/etc/udhcpc.d/50default: Adding DNS 147.231.10.9
/etc/udhcpc.d/50default: Adding DNS 8.8.8.8
done.
Starting system message bus: dbus.
Starting random number generator daemon.
Starting haveged: haveged: command socket is listening at fd 3
haveged: haveged starting up
haveged: haveged: ver: 1.9.13; arch: generic; vend: ; build: (gcc 10.2.0 CTV); collect: 128K
haveged: haveged: cpu: (VC); data: 16K (D); inst: 16K (D); idx: 11/40; sz: 15456/64452
haveged: haveged: tot tests(BA8): A:1/1 B:1/1 continuous tests(B): last entropy estimate 7.99981
haveged: haveged: fills: 0, generated: 0
Starting OpenBSD Secure Shell server: sshd
done.
Starting Xserver
Starting rpcbind daemon...done.
starting statd: done
starting Busybox HTTP Daemon: httpd... done.
X.Org X Server 1.20.9
X Protocol Version 11, Revision 0
Build Operating System: Linux
Current Operating System: Linux petalinux 5.10.0-xilinx-v2021.2 #1 SMP Tue Oct 12 09:30:57 UTC 2021 aarch64
Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk1p2 rw rootwait cma=512M
Build Date: 25 August 2020 03:40:19PM
Current version of pixman: 0.40.0
Before reporting problems, check http://wiki.x.org
to make sure that you have the latest version.
Markers: (--) probed, (**) from config file, (==) default setting,
(++) from command line, (!!) notice, (II) informational,
(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
(==) Log file: "/var/log/Xorg.0.log", Time: Fri Mar 9 12:36:46 2018
(==) Using config file: "/etc/X11/xorg.conf"
(==) Using system config directory "/usr/share/X11/xorg.conf.d"
(EE)
Fatal server error:
(EE) no screens found(EE)
(EE)
Please consult the The X.Org Foundation support
at http://wiki.x.org
for help.
(EE) Please also check the log file at "/var/log/Xorg.0.log" for additional information.
(EE)
(EE) Server terminated with error (1). Closing log file.
Starting internet superserver: inetd.
NFS daemon support not enabled in kernel
Init Start
Run init.sh from SD card
Load SD Init Script
User bash Code can be insered here and put init.sh on SD
Init End
Starting syslogd/klogd: done
Starting internet superserver: xinetd.
Starting watchdog daemon...done
Starting tcf-agent: OK
PetaLinux 2021.2 petalinux ttyPS0
root@petalinux:~# xinit: giving up
xinit: unable to connect to X server: Connection refused
xinit: server error
root@petalinux:~# ifconfig
eth0 Link encap:Ethernet HWaddr 80:1F:12:F2:B8:FF
inet addr:192.168.13.45 Bcast:192.168.13.255 Mask:255.255.255.0
inet6 addr: fe80::821f:12ff:fef2:b8ff/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:76 errors:0 dropped:0 overruns:0 frame:0
TX packets:17 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:8457 (8.2 KiB) TX bytes:2556 (2.4 KiB)
Interrupt:37
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
inet6 addr: ::1/128 Scope:Host
UP LOOPBACK RUNNING MTU:65536 Metric:1
RX packets:6 errors:0 dropped:0 overruns:0 frame:0
TX packets:6 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:380 (380.0 B) TX bytes:380 (380.0 B)
root@petalinux:~# cd /media/sd-mmcblk1p1/
root@petalinux:/media/sd-mmcblk1p1# ls
BOOT.BIN Image boot.scr init.sh krnl_vadd.xclbin system.dtb test_vadd
root@petalinux:/media/sd-mmcblk1p1#
root@petalinux:/media/sd-mmcblk1p1# ./test_vadd krnl_vadd.xclbin
INFO: Reading krnl_vadd.xclbin
Loading: 'krnl_vadd.xclbin'
Trying to program device[0]: edge
Device[0]: program successful!
TEST PASSED
root@petalinux:/media/sd-mmcblk1p1#
root@petalinux:/media/sd-mmcblk1p1#
root@petalinux:/media/sd-mmcblk1p1#
root@petalinux:/media/sd-mmcblk1p1# halt
Broadcast message from rootem is going down for system halt NOW!
INIT: Sending processes configured via /etc/inittab the TERM signal
root@petalinux:/media/sd-mmcblk1p1# Stopping haveged:
Stopping OpenBSD Secure Shell server: sshdstopped /usr/sbin/sshd (pid 666)
.
stopping Busybox HTTP Daemon: httpd... stopped httpd (pid 694)
done.
Stopping system message bus: dbus.
Stopping internet superserver: inetd.
stopping mountd: done
stopping nfsd: done
Stop.
Stopping syslogd/klogd: stopped syslogd (pid 708)
stopped klogd (pid 711)
done
Stopping tcf-agent: OK
Stopping internet superserver: xinetd.
Stopping XServer
stopping statd: done
Stopping random number generator daemon.
Stopping rpcbind daemon...
done.
Stopping S.M.A.R.T. daemon: smartd.
Deconfiguring network interfaces... done.
Stopping watchdog daemon...Sending all processes the TERM signal...
logout
Sending all processes the KILL signal...
Unmounting remote filesystems...
Deactivating swap...
Unmounting local filesystems...
[ 97.450106] reboot: Power down
|
- Petalinux boot,
- ifconfig to find assigned Ethernet address,
- test_vadd example executed to test the kernel execution,
- halt to proper terminate OS.
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Test 3: Create Vitis AI 2.0 BSP for large TE0821 module No. 8
Module No. 1: TE0821-01-2AE31KA with zu02cg-1e-4gb device has small PL part for implementation of the full size Vitis AI 2.0 DPU unit.
We will demonstrate how to implement the DPU unit and the DPU_TRD examole example on TE0821 module No. 8: TE0821-01-4DE31FL with xczu4ev-sfvc784-1-e device and 4gb memory.
Reuse of Petalinux files created for module No. 1.
First, we have to create new HW BSP for module No. 8.
Follow steps described for module No. 1: TE0821-01-2AE31KA with xczu2cg-sfvc784-1-e device and 4gb memory.
Extract bring up files to prepare HW design for module No. 8 in irectory:
~/work/TE0821_08_240/test_board
Expand PL HW design for module No. 8 up to the creation of .xsa archive in:
~/work/TE0821_08_240/test_board/vivado/test_board_4ev_1e_4gb.xsa
and fsbl.elf file in:
~/work/TE0821_08_240/test_board/prebuild/software/fsbl.elf
Follow same steps as described initially for Module No. 1.
Copy files (allready created for Module No. 1 extensible platform) to module No. 8 extensible platform directories:
~/work/TE0821_08_240/test_board_pfm/pfm/boot
~/work/TE0821_08_240/test_board_pfm/pfm/sd-dir
Copy these four files:
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Copy fsbl.elf file created for module No. 8 from:
~/work/TE0821_08_240/test_board/prebuild/software/fsbl.elf
to:
~/work/TE0821_08_240/test_board_pfm/pfm/boot/fsbl.elf
The directory
~/work/TE0821_08_240/test_board_pfm/pfm/boot
contains these five files, now:
- bl31.elf
- fsbl.elf
- pmufw.elf
- system.dtb
- u-boot.elf
Copy 3 files (created allready for Module No. 1) :
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Generation of Extensible Platform for module No. 8.
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In Ubuntu terminal, change the working directory to:
~/work/TE0821_08_240/test_board_pfm
Start the Vitis tool by executing
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$ vitis & |
In Vitis “Launcher”, set the workspace for the extensible platform compilation:
~/work/TE0821_08_240/test_board_pfm
Click on “Launch” to launch Vitis
Close Welcome page.
In Vitis, select in the main menu: File -> New -> Platform Project
Type name of the extensible platform: TE0821_08_240_pfm. Click Next.
Choose for hardware specification for the platform file:
~/work/TE0821_08_240/test_board/vivado/test_board_4ev_1e_4gb.xsa
In “Software specification” select: linux
In “Boot Components” unselect Generate boot components
(these components have been already generated by Vivado and PetaLinux design flow)
New window TE0821_08_240_pfm is opened.
Click on linux on psu_cortex53 to open window Domain: linux_domain
In “Description”: write xrt
In “Bif File” find and select the pre-defied option: Generate Bif
In “Boot Components Directory” select:
~/work/TE0821_08_240/test_board_pfm/pfm/boot
In “FAT32 Partition Directory” select:
~/work/TE0821_08_240/test_board_pfm/pfm/sd_dir
In Vitis IDE “Explorer” section, click on TE0821_08_240_pfm to highlight it.
Right-click on the highlighted TE0821_08_240_pfm and select build project in the open submenu. Platform is compiled in few seconds.
Close the Vitis tool by selection: File -> Exit.
Vits extensible platform TE0821_08_240_pfm has been created in the directory:
~/work/TE0821_08_240/test_board_pfm/TE0821_08_240_pfm/export/TE0821_08_240_pfm
The Vitis AI 2.0 HW platform for module No. 8 is created now.
Test 4: Vitis-AI Demo test on larger TE0821 module
This test implements simple AI demo to verify DPU integration to our custom extensible platform. This tutorial follows Xilix Vitis Tutorial for zcu104 with necessary fixes and customizations required for our case.
Create and Build Vitis Design
The Vitis AI Design with DPU will be gemerated by these steps:
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Create new directorytest_board_dpu_trd to test Vitis extendable flow example “dpu trd”
~/work/TE0821_08_240/test_board_dpu_trd
Current directory structure:
~/work/TE0821_01_240/test_board
~/work/TE0821_01_240/test_board_pfm
~/work/TE0821_01_240/test_board_test_vadd
~/work/TE0821_08_240/test_board
~/work/TE0821_08_240/test_board_pfm
~/work/TE0821_08_240/test_board_dpu_trd
Change working directory:
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$cd ~/work/TE0821_08_240/test_board_dpu_trd |
In Ubuntu terminal, start Vitis by:
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$ vitis & |
In Vitis IDE Launcher, select your working directory
~/work/TE0821_08_240/test_board_dpu_trd
Click on Launch to start Vitis.
Add Vitis-AI Repository to Vitis
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Open menu Window → Preferences
Go to Library Repository tab
Add Vitis-AI by clicking Add button and fill the form as shown below, use absolute path to your home folder in field "Location":
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Click Apply and Close.
| Info |
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Field "Location" says that the Vitis-AI repository from github has been cloned into ~/vitis_ai_2_0 folder, already in the stage of Petalinux configuration. It is the same Vitis-AI 2.0 package downloaded from the branch 2.0. Use the absolute path to your home directory. It depends on the user name. The user name in the figure is "devel". Replace it by your user name. |
Correctly added library appears in Libraries:
Open menu Xilinx → Libraries...
You can find there just added Vitis-AI library marked as "Installed".
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Create a Vitis-AI Design for our TE0821_01_240 custom platform
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Select File -> New -> Application project. Click Next.
Skip welcome page if it is shown.
Click on “+ Add” icon and select the custom extensible platform TE0821_08_240_pfm[custom] in the directory:
~/work/TE0821_08_240/test_board_pfm/TE0821_08_240_pfm/export/TE0821_08_240_pfm
Click Next.
In “Application Project Details” window type into Application project name: dpu_trd
Click Next.
In “Domain window” type (or select by browse):
“Sysroot path” (Sysroot of module No. 1 is reused):
~/work/TE0821_01_240/test_board_pfm/sysroots/cortexa72-cortexa53-xilinx-linux
“Root FS” (FS of module No. 1 is reused):
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/rootfs.ext4
“Kernel Image” (Kernel Image of module No. 1 is reused):
~/work/TE0821_01_240/test_board/os/petalinux/images/linux/Image
Click Next.
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In dsa folder, select: “DPU Kernel (RTL Kernel)”
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Click Finish
New project template is created.
In dpu_trd window menu “Active build configuration” switch from “SW Emulation” to “Hardware”.
| Info |
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| File dpu_conf.vh located at dpu_trd_kernels/src/prj/Vitis directory contains DPU configuration. |
Open file dpu_conf.vh and change in line 37:
`define URAM_DISABLE
to
`define URAM_ENABLE
and save modified file.
This modification is necessary for succsessfull implementation of the DPU on the zcu04-ev module with internal memories implemented in URAMs.
Go to dpu_trd_system_hw_link and double click on dpu_trd_system_hw_link.prj.
Remove sfm_xrt_top kernel from binary container by right clicking on it and choosing remove.
Reduce number of DPU kernels to one.
Configure connection of DPU kernels
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On the same tab right click on dpu and choose Edit V++ Options
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Click "..." button on the line of V++ Configuration Settings and modify configuration as follows:
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[clock] freqHz=200000000:DPUCZDX8G_1.aclk freqHz=400000000:DPUCZDX8G_1.ap_clk_2 [connectivity] sp=DPUCZDX8G_1.M_AXI_GP0:HPC0 sp=DPUCZDX8G_1.M_AXI_HP0:HP0 sp=DPUCZDX8G_1.M_AXI_HP2:HP1 |
Update packaging to add dependencies into SD Card
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Create a new folder img in your project in dpu_trd/src/app
Download image from provided link and place it to newly created folder dpu_trd/src/app/img.
Double click dpu_trd_system.sprj
Click "..." button on Packaging options
Enter "--package.sd_dir=../../dpu_trd/src/app"
Click OK.
Build DPU_TRD application
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In “Explorer” section of Vitis IDE, click on: dpu_trd_system[TE0821_08_240_pfm] to select it.
Right Click on: dpu_trd_system[TE0821_08_240_pfm] and select in the opened sub-menu:
Build project
Run DPU_TRD on Board
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Write sd_card.img to SD card using SD card reader.
The sd_card.img file is output of the compilation and packing by Vitis. It is located in directory:
~/work/TE0821_08_240/test_board_dpu_trd/dpu_trd_system/Hardware/package/
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| In Windows Pro 10 (or Windows 11 Pro) PC, inst all program Win32DiskImager for this task. Win32 Disk Imager can write raw disk image to removable devices. https://win32diskimager.org/ |
Boot the board and open terminal on the board either by connecting serial console connection, or by opening ethernet connection to ssh server on the board, or by opening terminal directly using window manager on board. Continue using the embedded board terminal.
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Detailed guide how to run embedded board and connect to it can be found in Run Compiled Example Application for Vector Addition. |
Check ext4 partition size by:
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root@petalinux:~# cd / root@petalinux:~# df . Filesystem 1K-blocks Used Available Use% Mounted on /dev/root 564048 398340 122364 77% / |
Resize partition
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root@petalinux:~# resize-part /dev/mmcblk1p2 /dev/mmcblk1p2 Warning: Partition /dev/mmcblk1p2 is being used. Are you sure you want to continue? parted: invalid token: 100% Yes/No? yes End? [2147MB]? 100% Information: You may need to update /etc/fstab. resize2fs 1.45.3 (14-Jul-2019) Filesystem at /dev/mmcblk1p2 is mounted on /media/sd-mmcblk1p2; o[ 72.751329] EXT4-fs (mmcblk1p2): resizing filesystem from 154804 to 1695488 blocks n-line resizing required old_desc_blocks = 1, new_desc_blocks = 1 [ 75.325525] EXT4-fs (mmcblk1p2): resized filesystem to 1695488 The filesystem on /dev/mmcblk1p2 is now 1695488 (4k) blocks long. |
Check ext4 partition size again, you should see:
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root@petalinux:~# df . -h Filesystem Size Used Available Use% Mounted on /dev/root 6.1G 390.8M 5.4G 7% / |
| Note |
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| The available size would be different according to your SD card size. |
Copy dependencies to home folder:
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# Libraries root@petalinux:~# cp -r /mnt/sd-mmcblk1p1/app/samples/ ~ # Model root@petalinux:~# cp /mnt/sd-mmcblk1p1/app/model/resnet50.xmodel ~ # Host app root@petalinux:~# cp /mnt/sd-mmcblk1p1/dpu_trd ~ # Images to test root@petalinux:~# cp /mnt/sd-mmcblk1p1/app/img/*.JPEG ~ |
Run the application from /home/root folder and you can observe that "bell pepper" receives highest score.
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root@petalinux:~# env XLNX_VART_FIRMWARE=/mnt/sd-mmcblk1p1/dpu.xclbin ./dpu_trd bellpeppe-994958.JPEG score[945] = 0.992235 text: bell pepper, score[941] = 0.00315807 text: acorn squash, score[943] = 0.00191546 text: cucumber, cuke, score[939] = 0.000904801 text: zucchini, courgette, score[949] = 0.00054879 text: strawberry, |
The resnet50 is trained for recognition of 1000 different objects.
The test board application reads the input figure and call the DPU with 8bit coefficients of the ResNet50 network.
The "bell pepper" object is recognised with high probability.
On board compilation of Vitis AI 2.0 demo
The application dpu_trd can be recompiled directly on the test board.
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chmod 777 ./build.sh ./build.sh Opencv4 OpenCV - Open Source Computer Vision Library root@petalinux:~# env XLNX_VART_FIRMWARE=/mnt/sd-mmcblk1p1/dpu.xclbin ./a.out bellpeppe-994958.JPEG score[945] = 0.992235 text: bell pepper, score[941] = 0.00315807 text: acorn squash, score[943] = 0.00191546 text: cucumber, cuke, score[939] = 0.000904801 text: zucchini, courgette, score[949] = 0.00054879 text: strawberry, |
The result of on compilation on test board is aplication a.out.
It provides identical results to the dpu_trd application compiled in Vitis in the PC Ubuntu Vitis AI environment.
Only the C++ SW part of the application can be compiled on the test board. The HW acceleration part (the dpu kernel)
has to be compiled in Ubuntu Vitis AI 2.0 framework (with Vivado).
Additional Vitis AI 2.0 demos
Many additional demos from the Vitis AI 2.0 library can be compiled on the test board and executed on the test board with identical dpu.
Vitis AI 2.0 demos work in several modes:
- From a image stored in a file with output in form of text to console or image displayed on the X11 desktop.
- From sequence of image stored in several files with output in form of text to console or images displayed on the X11 deskto
- From USB 2/3 www camera input video with output in form video displayed on the X11 remote desktop.
Use of USB 2/3 www camera input video requires the test board te0706-03 for correct recognition of the USB www camera.
Starting point for exploration of these Vitis AI 2.0 examples is this Xilinx www page.
Vitis AI 2.0 is Here! (xilinx.com)
TE0820 modules with smaller programmable logic area without URAMs (all xzcu2 and zxcu3 modules ) with 2GB of DDR4 are supported only for the extensible flow applications like the test_vadd demo.
Starting point for exploration of Vitis acceleration flow is Vitis Accel Examples' Repository (project templates are already downloaded in Vitis):
GitHub - Xilinx/Vitis_Accel_Examples at 2021.2
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decide free what's the best why to describe changes from standard reference design to get Vitis AI design. → Maybe add TCL code blox which automatically change the standard design? In case you has any question, let me know. |
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Overview
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