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Overview

OnlineRefer to https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TE0701 for downloadable version of this manual and otheradditional relatedtechnical documentsdocumentation canof be found at https://wiki.trenz-electronic.de/display/PD/TE0701 the product.

The Trenz Electronic TE0701 Carrier Board is a base-board for 4x5 4 x 5 SoMs, which exposes the MIO- and the PS/PL-pins of the SoM module's B2B-connector-pins to accessible connectors and provides a whole range of on-board components to test and evaluate Trenz Electronic 4x5 TE 4 x 5 SoMs.

See page "4 x 5 cm carriers" to get information about the SoMs supported by the TE0701 Carrier Board.

Main Components

Figure 1: 4x5 4 x 5 SoM carrier board TE0701-06

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1. HDMI Connector (1.4 HEAC Support)
2. Micro USB Connector (Device, Host or OTG Modes)

3. Pmod Connector for access to access Zynq-module's PL IO-bank pins (4 LVDS-pairs, max. VCCIO-voltage: VIOTA)

4. Pmod Connector Connector for access to access for Zynq-module's PL IO-bank pins (4 LVDS-pairs, max. VCCIO-voltage: FMC_VADJ)
5. User Push Button S2 ("RESTART" button by default)
6. User Push Button S1 ("RESET" button by default)
7. User LEDs (function mapping depends on firmware of System-Controller-CPLD)
8. Mini USB Connector (USB JTAG and UART Interface)
9. User 4-bit DIP Switch
10. VITA 57.1 compliant FMC LPC Connector with digitally programmable FMC VADJ Power Supply
11. Barrel jack for 12V Power Supply
12. ARM JTAG Connector (DS-5 D-Stream) - PJTAG to EMIO multiplexing needed
13. User 4-bit DIP Switch (provides the functionality to set voltage FMC_VADJ)
14. Pmod Connector (J1, max. VCCIO-voltage: 3.3V): mapped to 8 Zynq PS MIO0-bank-pins (MIO0, MIO9 to MIO15), 6 pins (MIO10 to MIO15) are additionally connected to TE0701 System-Controller-CPLD
15. RJ45 GbE Connector
16. SD Card Connector - Zynq SDIO0 Bootable SD port
17. Pmod Connector (J2, max. VCCIO-voltage: 3.3V): 6 pins (PX0 to PX5) can be multiplexed by Texas Instruments TXS02612RTWR SDIO Port Expander to MIO-pins of Zynq-module, 2 pins are connected to TE0701 System-Controller-CPLD (PX6 and PX7)
18. Jumper J18
19. Mini CameraLink Connector
20. Battery holder for CR1220 (RTC backup voltage)
21. Trenz 4x5 4 x 5 module Socket (3x Samtec LSHM Series Connectors)
22. Jumper J16, J17, J21
23. Jumper J9, J19, J20

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• Overvoltage-, undervoltage- and reversed- supply-voltage-protection
• Barrel jack for 12V power supply
• Carrier Board System-Controller-CPLD Lattice MachXO2 1200HC, programable by Mini-USB JTAG-Interface J7
• Zynq-module programable by ARM-JTAG-Interface-Connector (J15) or by System-Controller-CPLD via Mini-USB JTAG-Interface J7 or JTAG-Interface on FMC-Connector J10
• Mini CameraLink
• RJ45 Gigabit Ethernet MagJack with 2 integrated LEDs.
• FPGA Mezzanine Card (FMC) Connector J10 for acces to Zynq-Module's LVDS-pairs, operable with adjustable IO-voltage FMC_VADJ
  
• USB JTAG- and UART-Interface (FTDI FT2232HQ) with Mini-USB-Connector J7
• ADV7511 HDMI Transmitter with HDMI-Connector J4
  
• 8 x user LEDs routed to System-Controller-CPLD, 8 x red
• 2 x user-push button routed to System-Controller-CPLD; by default configured as system "RESET" and "RESTART" button (depends on CPLD-Firmware)
  
• 2 x 4-bit DIP-Switch for base-board-configuration (3 switches routed to System-Controller-CPLD, 3 switches to set voltage FMC_VADJ, 1 switch routed to Zynq-module (MIO0), 1 switch enables Mini-USB JTAG-Interface J7)
  
• PMOD-Connectors to access Zynq-Module's LVDS-pairs and MIO-Pins
  
• Micro SD card socket, can be used to boot system
• Micro-USB-Interface (J12) connected to Zynq-module (Device, Host or OTG modes)
• Trenz 4x5 4 x 5 module Socket (3 x Samtec LSHM series connectors)

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The TE0701 Carrier Board has on-board USB 2.0 High Speed to UART/FIFO IC FT2232HQ from FTDI. Channel A can be used as JTAG-Interface (MPSSE) to program the System-Controller-CPLD, Channel B can be used as UART-Interface routed to CPLD. There are also 4 6 additionally bus-lanes available for user-specific use. The FT2232HQ-Chip can also be used as FIFO in FT245 asynchronous mode.

There is also a standard 256 Byte EEPROM connected to the FT2232HQ-chip available to store custom configuration settings. EEPROM settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more informationsetting.

USB Interface

The TE0701 Carrier Board has two physical USB-connectors:

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Table 1: Configuration of DIP-switch S3

User

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Push-Buttons

On the TE0701 Carrier Board there are two push buttons (S1 and S2) and are routed to the System-Controller-CPLD and available to the user. The default mapping of the push buttons is as follows:

Table 2: Description of the standard functionalitys of user push-buttons S1 and S2

The functionality of the push buttons depends on the CPLD-firmware. For detailed information of the function of the push buttons, please refer to the documentation of the TE0701 System-Controller-CPLD.

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PHY LEDs are not connected directly to the module's B2B connectors as the 4x5 4 x 5 module have no dedicated PHY LED pins assigned. PHY LED's are connected to the TE0701 System-Controller-CPLD, that can route those LED's to some module's I/O Pins. In that case the CPLD has to map the PHY LEDs to corresponding pins.

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The on-board voltages 3.3V and 5.0V of the carrier board will be powered-up simultaneously after one single power-supply with a nominal voltage of 12V is plugged on connected to the barrel jack J10.

The on-board voltages 1.8V and 2.5V will be powered up after the module's 3.3V voltage-level has reached stable state and 3.3VOUT is available on the B2B-connector JB2, pins 9 and 11.

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The purpose of the jumpers and the DIP-switch S4 of the Carrier Board will be explained in the following sections.

Configuring VCCIO

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The Zynq-module's power supply is fixed to 5.0V!

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-voltage for PL IO-bank of mounted 4 x 5 SoM

The base-board supply-voltages for the PL IO-banks of the SoM are selectable by the jumpers J16, J17 and J21. The DIP-switch S4 sets the adjustable base-board supply-voltage FMC_VADJ.

Furthermore, the VCCIO13 supply voltage (bank 13) can be selected to be either identical to bank 33/34 (J21: 1-2, 3; jumper J16 removed) or to be FMC_VADJ (J21: 1, 2-3). Again, the latter is the default setting (i.e., VCCIO13=FMC_VADJ).

Note: The LVDS-pairs FMC_LA17 to FMC_LA33 (also PB0 to PB3 as well as Y0 to Y5) are routed to bank 13 of the Zynq-module, hence, the VCCIO13 supply voltage is chosen correspondingly by default!

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The FMC power supply on the TE0701 Carrier Board (i.e., FMC_VADJ) is user programmable via I2C.

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To enable FMC_VADJ on TE0701, bit 7 of the control-register should be set. Note that the I2C-Bus is shared with the I2C-Interface of the HDMI-Controller.

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S4-1

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FMC_VADJ Value

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Table 3: Switch S4 positions for fixed values of the FMC_VADJ voltage

Configuring 12V Power Supply Pin on the CameraLink Connector

Finally, a 12V power supply can be connected to pin 26 of the CameraLink by closing J18. However, this option is disabled by default (J18: OPEN).

Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes) 

The TE0701 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12; 13). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the overcurrent logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).

Additionally, the TE0701 carrier board is equipped with a second mini USB port (J7; see (8) in Figure 1) that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQ) and provides a USB-to-JTAG interface between a host PC and the TE0701 carrier board and the Zynq-module, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.

Summary of VCCIO-configuration via jumpers

There are two base board supply-voltages VIOTA and VIOTB connected to the 4x5 SoM's PL IO-banks. The supply-voltages have following pin assignments on B2B-connectors:

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base-board

supply-voltages

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base-board voltages and signals connected with

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Table 4: base-board supply-voltages VIOTA and VIOTB

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supported 4x5 SoMs vs

base-board VCCIO

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B33 (VCCIOC)

B34 (VCCIOB)

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B15 (VCCIOC)

B16 (VCCIOB)

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B66 (HP bank, VCCIOB)

B68 (HP bank, VCCIOC)

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B15 (VCCIOA)

B34 (VCCIOD)

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B15 (VCCIOA)

B35 (VCCIOD)

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B16 (VCCIOA)

B15 (VCCIOD)

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B16 (VCCIOA)

B15 (VCCIOD)

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B13 (VCCIOA)

B35 (VCCIOD)

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B13 (VCCIOA)

B35 (HP bank, VCCIOD)

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B35 (VCCIOA)

B13 (VCCIOD)

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B13 (VCCIOA)

B12 (VCCIOD)

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B64 (VCCIOA)

B67 (HP bank, VCCIOD)

Table 5: base-board supply-voltages VIOTA and VIOTB in conjunction with PL IO-bank voltages

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base-board supply-voltages vs

voltage-levels

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(J20: 1-2: additional decoupling-capacitor 100 µF)

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Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2, 3' means pins 1 and 2 are connected, 3 is open. 'Jx: 1, 2-3' means pins 2 and 3 are connected, 1 is open

Power On Reset (POR)

On the TE0701 the 5.0V and 3.3V power supply rails are generated by high performance DC-DC-converters from the external 12V supply. While the 3.3V plane supplies several on-board components (e.g., Lattice CPLD and FTDI Dual USB UART/FIFO IC), the 5V plane is mainly provided to power supply of the module to be carried (e.g., TE0720 Zynq SoC module). For the latter, however, special considerations must be taken (see TE0720 Power Supply). Therefore, the on-module system controller (SC) must be provided with information about the power-on-reset (POR) process, namely, the following control signals EN1, RESIN, and NOSEQ. And the SC provides, in turn, the status signal PGOOD down to the on-board System-Controller-CPLD.

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Table 3 shows the switch-configuration of the DIP-switch S4 to set the voltage FMC_VADJ:

Table 3: Switch S4 positions for fixed values of the FMC_VADJ voltage

Configuring 12V Power Supply Pin on the CameraLink Connector

Finally, a 12V power supply can be connected to pin 26 of the CameraLink by closing J18. However, this option is disabled by default (J18: OPEN).

Configuring Power Supply of the Micro USB Connector (Device, Host or OTG Modes) 

The TE0701 carrier board can be configured as a USB host. Hence, it must provide from 5.25V to 4.75V to the board side of the downstream connection (micro USB port on J12; 13). To provide sufficient power, a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface. If the output load exceeds the current-limit threshold, the TPS2051 limits the output current and pulls the overcurrent logic output (OC_n) low, which is routed to the on-board CPLD. The TPS2051 is put into operation by setting J19 CLOSED. J20 provides an extra 100µF decoupling capacitor (in addition to 10µF) to further stabilize the output signal. Moreover, a series terminating resistor of either 1K (J9: 1-2, 3) or 10K (J9: 1, 2-3) is selectable on the "USB-VBUS" signal. Both signals, USB-VBUS and VBUS_V_EN (that enables the TPS2051 on "high") are routed (as well as the corresponding D+/- data lines) via the on-board connector directly to the USB 2.0 high-speed transceiver PHY on the mounted SoM, which is, in turn, connected to the Zynq FPGA. In summary, the default jumper settings are the following: J9: 1-2, 3 (1K series terminating resistor); J19: CLOSED (TPS2051 in operation); J20: CLOSED (100 µF added).

Additionally, the TE0701 carrier board is equipped with a second mini USB port (J7; see (8) in Figure 1) that is connected to a "USB to multi-purpose UART/FIFO IC" from FTDI (FT2232HQ) and provides a USB-to-JTAG interface between a host PC and the TE0701 carrier board and the Zynq-module, respectively. Because it acts as a USB function device, no power switch is required (and only a ESD protection must be provided) in this case.

Summary of VCCIO-configuration via jumpers

There are two base board supply-voltages VIOTA and VIOTB connected to the 4 x 5 SoM's PL IO-banks. The supply-voltages have following pin assignments on B2B-connectors:

Table 4: base-board supply-voltages VIOTA and VIOTB

Following table describes how to configure the base-board supply-voltages by jumpers:

Table 7: Generation of PGOOD-Signal

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Technical Specifications

Absolute Maximum Ratings

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