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| Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
|---|
| 0 | 225 | GTH | - MGT_RX0_P
- MGT_RX0_N
- MGT_TX0_P
- MGT_TX0_N
| | - MGTHRXP0_225, Y2
- MGTHRXN0_225, Y1
- MGTHTXP0_225, AA4
- MGTHTXN0_225, AA3
|
| 1 | 225 | GTH | - MGT_RX1_P
- MGT_RX1_N
- MGT_TX1_P
- MGT_TX1_N
| | - MGTHRXP1_225, V2
- MGTHRXN1_225, V1
- MGTHTXP1_225, W4
- MGTHTXN1_225, W3
|
| 2 | 225 | GTH | - MGT_RX2_P
- MGT_RX2_N
- MGT_TX2_P
- MGT_TX2_N
| | - MGTHRXP2_225, T2
- MGTHRXN2_225, T1
- MGTHTXP2_225, U4
- MGTHTXN2_225, U3
|
| 3 | 225 | GTH | - MGT_RX3_P
- MGT_RX3_N
- MGT_TX3_P
- MGT_TX3_N
| | - MGTHRXP3_225, P2
- MGTHRXN3_225, P1
- MGTHTXP3_225, R4
- MGTHTXN3_225, R3
|
| 4 | 224 | GTH | - MGT_RX4_P
- MGT_RX4_N
- MGT_TX4_P
- MGT_TX4_N
| | - MGTHRXP0_224, AH2
- MGTHRXN0_224, AH1
- MGTHTXP0_224, AG4
- MGTHTXN0_224, AG3
|
| 5 | 224 | GTH | - MGT_RX5_P
- MGT_RX5_N
- MGT_TX5_P
- MGT_TX5_N
| | - MGTHRXP1_224, AF2
- MGTHRXN1_224, AF1
- MGTHTXP1_224, AF6
- MGTHTXN1_224, AF5
|
| 6 | 224 | GTH | - MGT_RX6_P
- MGT_RX6_N
- MGT_TX6_P
- MGT_TX6_N
| | - MGTHRXP2_224, AD2
- MGTHRXN2_224, AD1
- MGTHTXP2_224, AE4
- MGTHTXN2_224, AE3
|
| 7 | 224 | GTH | - MGT_RX7_P
- MGT_RX7_N
- MGT_TX7_P
- MGT_TX7_N
| | - MGTHRXP3_224, AB2
- MGTHRXN3_224, AB1
- MGTHTXP3_224, AC4
- MGTHTXN3_224, AC3
|
Table 3: MGT lanes
Below are listed MGT banks reference clock sources.
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