TE0841 TRM

Overview

The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 1 GByte of DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

Key Features

• Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
• 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
• 256 Mbit (32 MByte) QSPI Flash
• 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
  - User I/O: 60 x HR, 84 x HP
  - Serial transceiver: 8 x GTH lanes (TX/RX)
  - GT clock inputs: 2
• Clocking
  - Si5338 - 4 output PLLs, GT and PL clocks
  - 200 MHz LVDS oscillator
• All power supplies on-board, single power source operation
• Evenly spread supply pins for optimized signal integrity
• Size: 40 x 50 mm
• 3 mm mounting holes for skyline heat spreader
• Rugged for industrial applications

Additional assembly options for cost or performance optimization plus high volume prices are available on request.

Block Diagram

Figure 1: TE0841-01 block diagram.

Main Components

Figure 2: TE0841-01 main components.

1. Xilinx Kintex UltraScale FPGA, U1
2. Ultra performance oscillator @25.000000 MHz, U3
3. 12A PowerSoC DC-DC converter (0.95V), U14
4. 12A PowerSoC DC-DC converter (0.95V), U7
5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11
6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
11. Programmable quad clock generator, U2
12. 32 MByte QSPI Flash, U6
13. 4 Gbit DDR4 SDRAM, U4
14. 4 Gbit DDR4 SDRAM, U5
15. System Controller CPLD, U18
16. Low-dropout (LDO) linear regulator (MGTAUX), U9
17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Initial Delivery State

Table 1: TE0841-01 module initial delivery state of programmable on-board devices.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Table below lists bank number, bank type, B2B connection, I/O signal/LVDS pair count and power source for each FPGA PL I/O bank connected to the B2B connectors: 

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors.

For detailed information about the pin out, please refer to the Pin-out Tables. 

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: MGT lanes

Below are listed MGT banks reference clock sources.

Table 4: MGT reference clock sources.

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

Table 5: JTAG interface signals.

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins.

Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

Table 7: Quad SPI interface signals and connections.

I2C Interface

There are two PL bank 65 I/O pins (PLL_SCL and PLL_SDA) reserved as I²C bus connected to the Si5338 PLL quad clock generator. Default Si5338 PLL chip I²C bus slave address is 0x70.

Additionally, two PL bank 65 I/O pins (B65_SCL and B65_SDA) connected to the B2B connector JM1 can be used for external I²C connectivity, otherwise these pins are ordinary I/Os.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U18) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

Quad SPI Flash Memory

On-board QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q256A with 256-Mbit (32-MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Programmable PLL Clock

Module has Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate .

Table 8: Programmable quad PLL clock generator inputs and outputs.

Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 9: Reference clock signals.

On-board LEDs

Table 10: On-board LEDs.

Power and Power-On Sequence

Power Supply

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

Table 11: Typical power consumption.

 * TBD - To be determined.

Power-On Sequence

For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See also Xilinx datasheet DS892 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0720 module.

Power Rails

Table 12: Module power rails.

Board to Board Connectors

Variants Currently In Production

Table 13: Module variants.

Technical Specifications

Absolute Maximum Ratings

Table 14: Module absolute maximum ratings.

Recommended Operating Conditions

Table 15: Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

  
Figure 3: Module physical dimensions.

Weight

47 g - Plain module.

9 g - Set of bolts and nuts.

Revision History

Hardware Revision History

Table 16: Hardware revision history.

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 4: Module hardware revision number.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Jan Kumann	Initial document.

Table 17: Document change history.

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