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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
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0 | 505 | GTR |
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1 | 505 | GTR |
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2 | 505 | GTR |
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3 | 505 | GTR |
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Table 4: MGT lanes.
Below are listed MGT banks reference clock sources.
Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
B505_CLK0_P | 505 | B2B, JM3-31 | PS_MGTREFCLK0P_505, F23 | Supplied by the carrier board. |
B505_CLK0_N | 505 | B2B, JM3-33 | PS_MGTREFCLK0N_505, F24 | Supplied by the carrier board. |
B505_CLK1_P | 505 | U10, CLK2A | PS_MGTREFCLK1P_505, E21 | On-board Si5338A. |
B505_CLK1_N | 505 | U10, CLK2B | PS_MGTREFCLK1N_505, E22 | On-board Si5338A. |
B505_CLK2_P | 505 | N/A | PS_MGTREFCLK2P_505, C21 | Not connected. |
B505_CLK2_N | 505 | N/A | PS_MGTREFCLK2N_505, C22 | Not connected. |
B505_CLK3_P | 505 | U10, CLK1A | PS_MGTREFCLK3P_505, A21 | On-board Si5338A. |
B505_CLK3_N | 505 | U10, CLK1B | PS_MGTREFCLK3N_505, A22 | On-board Si5338A. |
Table 5: MGT reference clock sources.
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Date | Revision | Contributors | Description | ||||||||
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| v.3839 | Jan Kumann | MGT lanes section added. | ||||||||
2017-08-24 | v.36 | John Hartfiel | Correction in the "Key Features" section. | ||||||||
2017-08-21 | v.34 | John Hartfiel | "Initial delivery state" section updated. | ||||||||
2017-08-21 | v.33 | Jan Kumann |
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2017-08-18 | v.7 | John Hartfiel |
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2017-08-07 | v.5 | Jan Kumann | Initial version. |
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