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Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1, JB2 and JB3:
B2B Connector | Interfaces | Count of I/O's | Notes |
---|---|---|---|
JB1 | User I/O | 48 single ended or 24 differential | - |
GbE MagJack MDI | 8 | - | |
SD IO | 6 | - | |
MIO | 8 | - | |
SoM control signals | 5 | - | |
JB3 | GbE PHY RGMII | 18 | - |
USB2.0 (OTG, device and host mode) | 5 | - | |
JB2 | User I/O | 18 single ended | - |
48 single ended or 24 differential | - | ||
JTAG | 4 | - | |
SoM control signals | 1 | - | |
MagJack J3 LED's | 2 | - |
Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
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Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the connectors J5 and J6:
On-board Connector | Control Signals and Interfaces | Count of I/O's | Notes |
---|---|---|---|
J5 | User I/O | 18 single ended | - |
14 single ended or 7 differential | - | ||
MIO | 8 | - | |
MagJack J2 LED's | 2 | - | |
J6 | User I/O | 82 single ended or 41 differential | - |
SoM control signals | 2 | 'PGOOD', 'NOSEQ' |
Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.
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JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.
JTAG Signal | B2B Connector Pin | XMOD Header JX1 | Note |
---|---|---|---|
TCK | JB2-100 | JX1-4 | - |
TDI | JB2-96 | JX1-10 | - |
TDO | JB2-98 | JX1-8 | - |
TMS | JB2-94 | JX1-12 | - |
Table 3: JTAG interface signals.
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UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
UART Signal Schematic Name | B2B | XMOD Header JB3 | Note |
---|---|---|---|
MIO14 | JB1-91 | JX1-7 | UART-RX (receive line) |
MIO15 | JB1-86 | JX1-3 | UART-TX (transmit line) |
Table 4: UART interface signals.
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One of the SoM's I²C interface is routed to the on-board connector J5 and is available to the user for general purposes:
I²C Signal Schematic Name | B2B | On-board Connector | Note |
---|---|---|---|
MIO11 | JB1-94 | J5-27 | I²C data line |
MIO10 | JB1-96 | J5-28 | I²C clock line |
Table 5: I²C interface signals.
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The SD IO interface of the mounted SoM is routed to the on-board Texas Instruments TXS02612 SDIO port expander U4. This IC provides a necessary VDD/VCCIO translation between the MicroSD Card socket J4 (3.3V) and the SoM's Zynq device MIO-bank (1.8V):
SD IO Signal Schematic Name | B2B | Connected to | Note |
---|---|---|---|
SD_DAT0 | JB1-24 | U4-6 | SD IO data |
SD_DAT1 | JB1-22 | U4-7 | SD IO data |
SD_DAT2 | JB1-20 | U4-1 | SD IO data |
SD_DAT3 | JB1-18 | U4-3 | SD IO data |
SD_CLK | JB1-28 | U4-9 | SD IO clock |
SD_CMD | JB1-26 | U4-4 | SD IO command |
MIO0 | JB1-88 | J4-9 | Card Detect signal |
Table 6: SD IO interface signals.
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Following table gives an overview of the USB2.0 interface signals:
USB2.0 Signal Schematic Name | B2B | Connected to | Note |
---|---|---|---|
OTG-D_N | JB2-48 | J11-2, (J10-2) | USB2.0 data |
OTG-D_P | JB2-50 | J11-3, (J10-3) | USB2.0 data |
OTG-ID | JB2-52 | J11-4 | Ground this pin for A-Device (host), left floating this pin for B-Device (peripheral). |
VBUS_V_EN | JB2-54 | U3, pin 4 | Enable USB-VBUS. |
USB-VBUS | JB2-56 | J11-1, (J10-1) | USB supply voltage in Host mode. |
Table 7: USB2.0 interface signals and connections.
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The GbE MegJack J2 has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the GbE PHY.
PHY U6 pins | B2B-pin | Notes |
---|---|---|
ETH-MDC/ETH-MDIO | JB3-49, JB3-51 | - |
PHY_LED0 | - | Connected to GbE MagJack J2 LED0 (green). Also connected to J5-24 (PHY_LED0_CON). |
PHY_LED1 | - | Connected to GbE MagJack J2 LED1 (green). Also connected to J5-23 (PHY_LED1_CON). |
PHY_INT | JB3-33 | - |
CONFIG | JB3-60 | - |
CLK125 | JB3-32 | PHY Clock (125 MHz) output. |
ETH-RST | JB3-53 | - |
RGMII | JB3-37 - JB-44, JB3-47, JB3-57 - JB-59 | Reduced Gigabit Media Independent Interface. 12 pins. |
SGMII | - | Serial Gigabit Media Independent Interface. Not connected. |
MDI | - | Media Dependent Interface. Connected to Gigabit Ethernet MagJack J2. |
Table 8: GbE interface signals and connections.
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There is usually a corresponding Gigabit Ethernet PHY on 4 x 5 SoMs (e.g. TE0715 or TE0720), which can be used in conjunction with the baseboard MagJack J3.
GbE PHY Signal Schematic Name | B2B | Connected to | Notes |
---|---|---|---|
PHY_MDI0_P | JB1-3 | J3-2 | - |
PHY_MDI0_N | JB1-5 | J3-3 | - |
PHY_MDI1_P | JB1-9 | J3-4 | - |
PHY_MDI1_N | JB1-11 | J3-5 | - |
PHY_MDI2_P | JB1-15 | J3-6 | - |
PHY_MDI2_N | JB1-17 | J3-7 | - |
PHY_MDI3_P | JB1-21 | J3-8 | - |
PHY_MDI3_N | JB1-23 | J3-9 | - |
ETH_LED1 | JB2-90 | Green MegJack J3 LED | - |
ETH_LED2 | JB2-99 | Green MegJack J3 LED | - |
Table 9: RJ45 GbE MagJack signals and connections.
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Following table describes the signals and interfaces of the XMOD header JX1:
JX1 pin | Signal Schematic Net Name | B2B | Note |
---|---|---|---|
C (pin 4) | TCK | JB2-100 | - |
D (pin 8) | TDO | JB2-98 | - |
F (pin 10) | TDI | JB2-96 | - |
H (pin 12) | TMS | JB2-94 | - |
A (pin 3) | MIO15 | JB1-86 | UART-TX (transmit line) |
B (pin 7) | MIO14 | JB1-91 | UART-RX (receive line) |
E (pin 9) | - | - | not used |
G (pin 11) | - | - | not used |
Table 10: XMOD header signals and connections.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the mounted SoM's 'VCCJTAG' (pin JB2-92). Set the DIP-switch with the setting:
XMOD DIP-switches | Position |
---|---|
Switch 1 | ON |
Switch 2 | OFF |
Switch 3 | OFF |
Switch 4 | ON |
Table 11: XMOD adapter board DIP-switch positions for voltage configuration.
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Table below describes DIP-switch S1 settings for configuration of the mounted SoM:
Switch | Signal Name | ON | OFF | Notes |
---|---|---|---|---|
S1-1 | - | - | - | Not connected. |
S1-2 | PROGMODE | JTAG enabled for programing mounted SoM's Zynq-SoC. | JTAG enabled for programing mounted SoM's SC-CPLD. | - |
S1-3 | MODE | Drive SoM SC CPLD pin 'MODE' low. | Leave SoM SC CPLD pin 'MODE' open. | Boot mode configuration, if supported by SoM. (Depends also on SoM's SC-CPLD firmware). |
S1-4 | EN1 | Drive SoM SC CPLD pin 'EN1' low. | Drive SoM SC CPLD pin 'EN1' high. | Usually used to enable/disable FPGA core-voltage supply. (Depends also on SoM's SC CPLD firmware). Note: Power-on sequence will be intermitted if S1-4 is set to OFF and if functionality is supported by SoM. |
Table 12: DIP-switch S1 SoM configuration settings.
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Following table describes how to configure the VCCIO of the SoM's PL I/O-banks with jumpers:
Supply Voltage by Jumper | Supply Voltage by 0-Ohm Resistor | Supply Voltage by Connector J6 | ||||
---|---|---|---|---|---|---|
Voltage Level | 1.8V | 3.3V | 1.8V | 3.3V | Variable | |
VCCIOA | J10: 1-2, 3 | J10: 1, 2-3 | - | R20 | J6 pin B32 | |
VCCIOB | J11: 1-2, 3 | J11: 1, 2-3 | R29 | R21 | - | |
VCCIOC | J12: 1-2, 3 | J12: 1, 2-3 | R30 | R22 | J6 pin B1 |
Table 13: VCCIO jumper settings.
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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
5VIN | TBD* |
Table 14: Typical power consumption.
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The voltage direction of the power rails is from board and on-board connectors' view:
Module Connector (B2B) Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
JB1 | 3.3V | Out | 2, 4, 6, 14, 16 | 3.3V module supply voltage |
VCCIOA | Out | 10, 12 | PL IO-bank VCCIO | |
M1.8VOUT | In | 40 | 1.8V module output voltage | |
VBAT | Out | 80 | RTC buffer voltage | |
JB2 | 1.8V | Out | 2, 4 | 1.8V module supply voltage |
VCCIOB | Out | 6 | PL IO-bank VCCIO | |
VCCIOC | Out | 8, 10 | PL IO-bank VCCIO | |
M3.3VOUT | In | 9, 11 | 3.3V module output voltage | |
VCCJTAG | In | 92 | 3.3V JTAG VCCIO | |
JB3 | USB-VBUS | Out | 56 | USB Host supply voltage |
Table 15: Power pin description of B2B module connector.
On-board Connector Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J5 | 3.3V | Out | 6, 45 | 3.3V module supply voltage |
M3.3VOUT | In | 5, 46 | 3.3V module output voltage | |
J6 | VCCIOA | Out | B32 | PL IO-bank VCCIO |
VCCIOC | Out | B1 | PL IO-bank VCCIO | |
M3.3VOUT | In | C32 | 3.3V module output voltage | |
3.3V | Out | C31 | 3.3V module supply voltage | |
5VIN | In | A1, A2 | Carrier Board supply power |
Table 16: Power Pin description of on-board connector.
Jumper / Header Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J10 | VCCIOA | Out | 2 | - |
1.8V | Out | 1 | - | |
M3.3VOUT | Out | 3 | - | |
J11 | VCCIOB | Out | 2 | - |
1.8V | Out | 1 | - | |
M3.3VOUT | Out | 3 | - | |
J12 | VCCIOC | Out | 2 | - |
1.8V | Out | 1 | - | |
M3.3VOUT | Out | 3 | - |
Table 17: Power Pin description of VCCIO selection jumper pin header.
Main Power Jack and Pins Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J1 | 5VIN | In | - | - |
J6 | 5VIN | In | A1, A2 | '5VIN' power supply to the Carrier Board as alternative to J1 |
J9 | VBAT | In | 1 | Attention: Pin 2 connected to ground. VBAT voltage connected on this pin cause short-circuit. |
Table 18: Main Power jack and pins description.
Peripheral Socket Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J7 / J8 | USB-VBUS | Out | 1 | USB2.0 Type A socket / Micro USB2.0 B socket |
J4 | M3.3VOUT | Out | 4 | MikroSD Card socket VDD |
Table 19: Power pin description of peripheral connector.
XMOD Header Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
JX1 | 3.3V | - | 5 | not connected |
VIO | Out | 6 | connected to 'VCCJTAG' (pin JB2-92) |
Table 20: Power pin description of XMOD/JTAG Connector.
Board to Board Connectors
Include Page | ||||||
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Variants Currently In Production
Module Variant | Operating Temperature | USB2.0 Socket | Temperature Range |
---|---|---|---|
TE0706-02 | -40°C to +85°C | USB2.0 Type A socket fitted | Industrial |
TE0706-D-02 | -40°C to +85°C | Micro USB2.0 Type B socket fitted | Industrial |
Table 21: Board variants.
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
5VIN supply voltage | -0.3 | 7 | V | MP5010A, EN6347QI, EN5311QI data sheet |
Storage temperature | -55 | +85 | °C | Marvell 88E1512 data sheet |
Table 22: Module absolute maximum ratings.
Recommended Operating Conditions
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
5VIN supply voltage | 4.75 | 5.25 | V | USB2.0 specification concerning 'VBUS' voltage |
Operating temperature | -40 | +85 | °C | - |
Table 23: Module recommended operating conditions.
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Hardware Revision History
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2016-06-28 | 01 |
| - | TE0706-01 |
- | 02 |
| - | TE0706-02 |
Table 24: Module hardware revision history.
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Date | Revision | Contributors | Description | ||||||||
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| Ali Naseri |
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2017-07-06 | v.52 | Ali Naseri, Jan Kumann |
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2017-01-06 | v.1 | Ali Naseri |
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Table 25: Document change history.
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