Page History

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Revision History

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Design supports following carriers:

Additional HW Requirements:

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For general structure and of the reference design, see Project Delivery

Design Sources

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Design supports following carriers:

Additional HW Requirements:

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For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

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Additional Sources

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Prebuilt

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<table width="100%">
<tr> <th>File                                   </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Reference Design is available on:

• TE0??? TE0725 "Test Board" Reference Design

Design Flow

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TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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7. Press 0 and enter for minimum setup
8. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
9. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
10. Create HDF and export to prebuilt folder
    
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
       Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
11. Create Linux (uboot.elf and image.ub) with exported HDF
    
    1. HDF is exported to "prebuilt\hardware\<short name>"
       Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
       1. Use TE Template from /os/petalinux
          Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
12. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
       Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
13. Generate Programming Files with HSI/SDK
    
    1. Run on Vivado TCL: TE::sw_run_hsi
       Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
       Note: See SDK Projects

SDSoC (only tested on Win OS)

1. Generate Platform Project or use prebuilt from download
2. ...

Launch

Programming

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
4. Copy image.ub on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

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• For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt

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• Depends on Carrier, see carrier TRM.

1. Copy Application (hello_te0711.elf) into \firmware\microblaze_0\
2. Regenerate Design:
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
   2. (alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.

Launch

Programming

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

1. Connect JTAG and power on PCB
2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
3. Type on Vivado Console: TE::pr_program_flash_mcsfile
   Note: Alternative use SDK or setup Flash on Vivado manually
4. Reboot (if not done automatically)

SD

Not used on this Example

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JTAG

Not used on this Example.

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1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)Select SD Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
3. Power On PCB

   Note:

   1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

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1. FPGA Loads Bitfile from Flash

UART

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root

Vivado HW Manager

SI5338_CLK0 Counter: 

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1. 1. : 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Uart Console:
   Hello TE0725 will run on endless loop.

System Design - Vivado

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Block Design

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Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUECFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_VOLTAGEADDR 3.3YES [current_design]
set_property CFGBVS VCCOBITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESSM1PIN TIMESTAMPPULLNONE [current_design]

Design specific constrain

set_property PACKAGE_PIN K2BITSTREAM.CONFIG.M2PIN PULLNONE [get_ports {fclk[0]}current_design]
set_property IOSTANDARD LVCMOS18BITSTREAM.CONFIG.M0PIN PULLNONE [get_ports {fclk[0]}]current_design]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

Software Design - SDK/HSI

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Hello World as endless loop.

Additional Software

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