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Table of contents

Overview

 MicroBlaze Design with Hello TE0725 example in endless loop.

Key Features

  • MicroBlaze
  • QSPI
  • I2C
  • UART

Revision History

DateVivadoProject BuiltAuthorsDescription
2018-08-092018.2TE0725-test_board_noprebuilt-vivado_2018.2-build_02_20180809122533.zip
TE0725-test_board-vivado_2018.2-build_02_20180809122018.zip
John Hartfiel
  • 2018.2 update
2018-03-182017.4TE0725-test_board_noprebuilt-vivado_2017.4-build_07_20180319171220.zip
TE0725-test_board-vivado_2017.4-build_07_20180319171209.zip
John Hartfiel
  • Board Part update reference link only
2018-03-162017.4TE0725-test_board_noprebuilt-vivado_2017.4-build_07_20180316163402.zip
TE0725-test_board-vivado_2017.4-build_07_20180316163351.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------

Requirements

Software

SoftwareVersionNote
Vivado2018.2needed
SDK2018.2needed

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
 TE0725-03-15-1C 15_1c REV01, REV02, REV03---328MB HypeRAM
 TE0725-03-35-2C 35_2c  REV01, REV02, REV03---328MB HypeRAM
 TE0725-03-100-2C 100_2c  REV01, REV02, REV03---328MB HypeRAM
TE0725-03-100-2CF100_2c REV01, REV02, REV03---328MB HypeRAMPOF assembled
TE0725-03-100-2I9100_2i REV01, REV02, REV03---328MB HypeRAM

Design supports following carriers:

Carrier ModelNotes
---

Additional HW Requirements:

Additional HardwareNotes
TE0790 JTAG Programmer It's not recommended to use TE0790 for power supply( TE0790 TRM#PowerandPower-OnSequence)
External power supply

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

TypeLocationNotes

Prebuilt

File

File-Extension

Description

BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
  7. Copy Application (hello_te0711.elf) into \firmware\microblaze_0\
  8. Regenerate Design:
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
    2. (alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.

Launch

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile
    Note: Alternative use SDK or setup Flash on Vivado manually
  4. Reboot (if not done automatically)


SD

Not used on this Example.

JTAG

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Open Vivado HW Manager
  4. Program Bitfile

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Power On PCB (Do not restart, if you use Bitfile programming)

    Note: FPGA Loads Bitfile from Flash

UART

  1. Open Serial Console (e.g. putty)
    1. Speed: 9600
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Uart Console:
    Hello TE0725 will run on endless loop.


System Design - Vivado

Block Design

Constrains

Basic module constrains

_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain


Software Design - SDK/HSI

For SDK project creation, follow instructions from:

SDK Projects

Application

hello_te0725

Hello World as endless loop.


Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

v.9



  • 2018.2 update

v.8John Hartfiel
  • Board Part Documentation update
  • Typo correction UART Speed
2018-03-16

v.5

John Hartfiel
  • 2017.4 release
2018-03-12v.1
  • Initial release

All

Legal Notices

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Technology Licenses

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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