Page History
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- Four SFP+ 10Gb ports
- HPC FMC connector
- Low jitter programmable clock generator
- Intel(Altera) Max10 FPGA 10M08SAU169C8G
- Status LED (green)
Block Diagram
Figure 1: TEF0008-01 block diagram.
Main Components
Figure 2: TEF0008-01 FMC overview.
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The MAX10 FPGA boots form its internal configuration flash memory, which is programmable via JTAG (J3).
Signals, Interfaces and Pins
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There is a Silicon Labs I2C programmable clock generator on-board (Si5345A, U2) to generate reference clocks for the module. Programming can be done using I2C via PIN header J1. The I2C bus is also routed to the MAX10 FPGA.
Si5345A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN0 | Reference input clock. | U1 | Input | 25.000000 MHz oscillator, Si8208AI |
IN1 | - | Not connected. | Input | Not used. |
IN2 | - | Not connected. | Input | Not used. |
IN3 | CLK2 | J2-K4/K5 | Input | HPC FMC configured as C2M clock. |
A1 | - | GND | Input | I2C slave device address LSB. |
XAXB | - | Y1 | Input | 54.0000 MHz XTAL CX3225SB |
OUT0 | CLKPLL2F | U5-H6/G5 | Output | FPGA bank 2. |
OUT1 | - | Not connected. | Output | Not used. |
OUT2 | GBTCLK1 | J2-B20/B21 | Output | M2C via HPC FMC. |
OUT3 | - | Not connected. | Output | Not used. |
OUT4 | - | Not connected. | Output | Not used. |
OUT5 | - | Not connected. | Output | Not used. |
OUT6 | - | Not connected. | Output | Not used. |
OUT7 | GBTCLK0 | J2-D4/D5 | Output | M2C via HPC FMC. |
OUT8 | CLK0 | J2-H4/H5 | Output | M2C via HPC FMC. |
OUT9 | CLK1 | J2-G2/G3 | Output | M2C via HPC FMC. |
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Overview
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