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Template Revision 2.0 - on construction

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"

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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_x
        titleFigure x: Text
        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use

        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
      • Scroll Title
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        titleTable x: Text

        Scroll Table Layout
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        ExampleComment
        12
  • ...

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Scroll Title
anchorTable_1
titleTable 1: Initial delivery state of programmable devices on the module.

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Storage device name

Content

Notes

..

..

..
OTP Flash areaEmptyNot programmed.

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Front panel USB-C Interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

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Scroll Title
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titleTable x: FTDI Signals

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FT601Q SignalFPGA Pin
FIFO_CLK
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See FT600Q-FT601Q

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See FT600Q-FT601Q IC Datasheet for interface details.

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The TEC0850 board has 30 MGT lines routed to backplane connectors.

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anchor

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Table_x
titleTable x: MGT Banks

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BankConnectorLanes
PL 128J4G

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and J4H4
PL 129J5A and J5B4
PL 130J5C and J5D4
PL 230J4G and J4H4
PL 229J5A and J5B4
PL 228J5C and J5D4
PS 505J1A4

MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.

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Main IO interfaces are shown on the image below.


PS MIO Configuration

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anchorTable_x
titleTable x: Default MIO Configuration

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MIOInterface
MIO 0...12QSPI Flash Memory
MIO 20...21I2C 1
MIO 22...23UART 0
MIO 26...37GEM 0
MIO 46...51SD 1
MIO 52...63USB 0
MIO 64...75USB 1
MIO 76...77MDIO 0

Table 10: Default MIO Configuration

MAX10 System Controller

System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.

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The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.

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Scroll Title
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titleTable x: SI5345 I2C address

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I2C addressChipDescription
0x69U14 Si5345Clock generator and distributor

Oscillators

FTDIs

FT2232H

FT601Q-B-T

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The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.

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Scroll Title
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titleTable x: EEPROMs I2C Addresses

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I2C addressChipDescription
0x50U63 24AA128T-I/ST128K Serial EEPROM
0x53U64 24AA025E48T-I/OT2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity

USB PHY

Gigabit Ethernet PHY

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Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate. 


DIP-Switches

S1

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titleTable x: LEDs

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SwitchDescription
1Boot Mode 0
2Boot Mode 1
3Boot Mode 2
4Boot Mode 3

See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are

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Scroll Title
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titleTable x: Recommended Boot Modes

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Boot ModeSW1:4SW1:3SW1:

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2SW1:1
JTAG Boot ModeONONONON
Quad-SPIONONONOFF
SD CardONONOFFOFF

S2

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titleTable x: S2 DIP Switch

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SwitchDescription
1SC JTAGEN
2EEPROM WP (Write protect)
3FPGA PUDC
4SC Switch (Reserved for

...

future use)

Buttons

LEDs

Scroll Title
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titleTable x: LEDs

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Buttons

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LEDSignalChipPinDescription
Front panel LED 1 (Red)LED_FP_1FPGA U1AF15PL User defined LED
Front panel LED 2 (Green)LED_FP_2FPGA U1AG15PL User defined LED
Front panel LED 3 (Green)LED_FP_3FPGA U1AE15PL User defined LED
Front panel LED 4 (Green)LED_FP_4SC U18M4Power Good

Power and Power-On Sequence

...

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.Electronic Wiki FAQ.


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titleTable x: Typical power consumption.

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Power InputTypical Current

TBD*

Table : Typical power consumption. 

Power Distribution Dependencies

...

Voltage Monitor Circuit

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Voltages

Technical Specifications

Absolute Maximum Ratings

Table x: Module absolute maximum ratings.
Scroll Title
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titleTable x: Module absolute maximum ratings.

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title

ParameterMinMaxUnitsReference Document










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Scroll Title
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titleTable x: Module absolute maximum ratings.ratings.

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ParameterMinMaxUnitsReference Document










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Scroll Title
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titleTable x: Shop Overview

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Trenz shop TE0xxx overview page
English pageGerman page


Revision History

Hardware Revision History

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DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes








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titleTable x: Document change history.

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DateRevision

Contributor

Description

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dateFormatyyyy-MM-dd

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  • change list
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