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Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| ADBUS0 | G9 | 3V_D | ||
| ADBUS1 | F10 | 3V_D | ||
| ADBUS2 | E10 | 3V_D | ||
| ADBUS3 | D9 | 3V_D | ||
| AVDD_SHDN | G10 | 3V_D | ||
| BCBUS0 | D12 | 3V_D | ||
| BCBUS1 | E13 | 3V_D | ||
| BCBUS2 | E12 | 3V_D | ||
| BCBUS3 | F13 | 3V_D | ||
| BCBUS4 | F12 | 3V_D | ||
| BDBUS0 | B11 | 3V_D | ||
| BDBUS1 | A12 | 3V_D | ||
| BDBUS2 | B12 | 3V_D | ||
| BDBUS3 | C11 | 3V_D | ||
| BDBUS4 | B13 | 3V_D | ||
| BDBUS5 | C12 | 3V_D | ||
| BDBUS6 | C13 | 3V_D | ||
| BDBUS7 | D11 | 3V_D | ||
| CONF_DONE | C5 | 3V_D | ||
| DET_BPR | H2 | 3V_D | ||
| DET_RIO | H3 | 3V_D | ||
| DONE | N3 | PS_1V8 | ||
| EN_3V3 | C10 | 3V_D | ||
| EN_DAC1 | E6 | 3V_D | ||
| EN_DAC2 | E8 | 3V_D | ||
| EN_DAC3 | B6 | 3V_D | ||
| EN_DAC4 | A6 | 3V_D | ||
| EN_DDR | G13 | 3V_D | ||
| EN_FPD | L12 | 3V_D | ||
| EN_LPD | J13 | 3V_D | ||
| EN_PSGT | B9 | 3V_D | ||
| ERR_OUT | G5 | PS_1V8 | ||
| ERR_STATUS | H6 | PS_1V8 | ||
| F_TCK | N2 | PS_1V8 | ||
| F_TDI | M1 | PS_1V8 | ||
| F_TDO | K1 | PS_1V8 | ||
| F_TMS | J1 | PS_1V8 | ||
| F1PWM | H10 | 3V_D | ||
| F1SENSE | J9 | 3V_D | ||
| FTDI_RST | E9 | 3V_D | ||
| GA0 | F8 | 3V_D | ||
| GA0_R | F9 | 3V_D | ||
| GA1 | A2 | 3V_D | ||
| GA1_R | B2 | 3V_D | ||
| GA2 | A3 | 3V_D | ||
| GA2_R | B3 | 3V_D | ||
| GA3 | A4 | 3V_D | ||
| GA3_R | B4 | 3V_D | ||
| IEEE_SW_NC | C9 | 3V_D | ||
| IEEE_SW_NO | A11 | 3V_D | ||
| INIT_B | L2 | PS_1V8 | ||
| JTAGEN | E5 | 3V_D | ||
| LED_FP_4 | M4 | 3.3V | ||
| LP_GOOD | H13 | 3V_D | ||
| M10_RST | A7 | 3V_D | ||
| M10_RX | C2 | 3V_D | ||
| M10_TX | B1 | 3V_D | ||
| MAX_IO1 | N8 | 3.3V | ||
| MAX_IO10 | M10 | 3.3V | ||
| MAX_IO2 | N7 | 3.3V | ||
| MAX_IO3 | M9 | 3.3V | ||
| MAX_IO4 | M8 | 3.3V | ||
| MAX_IO5 | M12 | 3.3V | ||
| MAX_IO6 | M13 | 3.3V | ||
| MAX_IO7 | N9 | 3.3V | ||
| MAX_IO8 | N10 | 3.3V | ||
| MAX_IO9 | M11 | 3.3V | ||
| MIO22 | M3 | PS_1V8 | ||
| MIO23 | M2 | PS_1V8 | ||
| MIO24 | L3 | PS_1V8 | ||
| MIO25 | H5 | PS_1V8 | ||
| MR | K10 | 3V_D | ||
| N.C. | J5 | 3.3V | ||
| N.C. | J6 | 3.3V | ||
| N.C. | J7 | 3.3V | ||
| N.C. | J8 | 3.3V | ||
| N.C. | K5 | 3.3V | ||
| N.C. | K6 | 3.3V | ||
| N.C. | K7 | 3.3V | ||
| N.C. | K8 | 3.3V | ||
| N.C. | L4 | 3.3V | ||
| N.C. | L5 | 3.3V | ||
| N.C. | M5 | 3.3V | ||
| N.C. | M7 | 3.3V | ||
| N.C. | N4 | 3.3V | ||
| N.C. | N5 | 3.3V | ||
| N.C. | N6 | 3.3V | ||
| N.C. | L10 | 3.3V | ||
| N.C. | L11 | 3.3V | ||
| N.C. | N12 | 3.3V | ||
| nCONF | E7 | 3V_D | ||
| nSTATUS | C4 | 3V_D | ||
| ON_GT_L | J12 | 3V_D | ||
| ON_GT_R | K12 | 3V_D | ||
| PG_DDR | H8 | 3V_D | ||
| PG_GT_L | H9 | 3V_D | ||
| PG_GT_R | G12 | 3V_D | ||
| PG_PL | L13 | 3V_D | ||
| PG_PSGT | K11 | 3V_D | ||
| PLL_RST | K2 | PS_1V8 | ||
| PROG_B | J2 | PS_1V8 | ||
| PSON | D6 | 3V_D | ||
| RP_SCL | E1 | 3V_D | ||
| RP_SDI | G4 | 3V_D | ||
| RP_SDO | F4 | 3V_D | ||
| RP_SL | F1 | 3V_D | ||
| RST | B5 | 3V_D | ||
| RST_PRST | A8 | 3V_D | ||
| RST_PRST_R | B10 | 3V_D | ||
| RST_R | D8 | 3V_D | ||
| SATA_SCL | G2 | 3V_D | ||
| SATA_SDI | F6 | 3V_D | ||
| SATA_SDO | F5 | 3V_D | ||
| SATA_SL | G1 | 3V_D | ||
| SMB_SCL | E3 | 3V_D | ||
| SMB_SCL_R | E4 | 3V_D | ||
| SMB_SDA | C1 | 3V_D | ||
| SMB_SDA_R | D1 | 3V_D | ||
| SRST_B | H4 | PS_1V8 | ||
| SW4 | A5 | 3V_D | ||
| SYSEN | D7 | 3V_D | ||
| USR_BTN | J10 | 3V_D | ||
| WAKE | A9 | 3V_D | ||
| WAKE_R | A10 | 3V_D |
| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| FTDI_RXD | in | UART receive data from FTDI | ||
| FTDI_TXD | out | UART transmit data to FTDI | ||
| MIO22 | out | UART receive data to FPGA | ||
| MIO23 | in | UART receive data from FPGA | ||
| ZYNQ_TDO | in | FPGA JTAG TDO | ||
| ZYNQ_TCK | out | FPGA JTAG TCK | ||
| ZYNQ_TDI | out | FPGA JTAG TDI | ||
| ZYNQ_TMS | out | FPGA JTAG TMS | ||
| ADBUS0 | in | FTDI JTAG TCK | ||
| ADBUS1 | in | FTDI JTAG TDI | ||
| ADBUS2 | out | FTDI JTAG TDO | ||
| ADBUS3 | in | FTDI JTAG TMS | ||
| USB_BTN | in | Front panel button | ||
| LED4 | out | Front panel LED4 | ||
| MR | out | Supervisor Reset output | ||
| SRST_B | out | FPGA SRST_B | ||
| FTDI_RST | out | FPGA RST_B | ||
| PLL_RST | out | Clock chip Reset | ||
| EN_DAC1 | out | DAC1 Power Enable | ||
| EN_DAC2 | out | DAC2 Power Enable | ||
| EN_DAC3 | out | DAC3 Power Enable | ||
| EN_DAC4 | out | DAC4 Power Enable | ||
| EN_FPD | out | FPD Power Enable | ||
| EN_LPD | out | LPD Power Enable | ||
| EN_DDR | out | DDR Power Enable | ||
| EN_PSGT | out | PSGT Power Enable | ||
| ON_GT_L | out | GT_L Power Enable | ||
| ON_GT_R | out | GT_R Power Enable | ||
| PG_PSGT | in | PSGT Power Good | ||
| LP_GOOD | in | LP Power Good | ||
| PG_GT_L | in | GT_L Power Good | ||
| PG_GT_R | in | GT_R Power Good | ||
| PG_PL | in | PL Power Good | ||
| PG_DDR | in | DDR Power Good | ||
| F1PWM | out | FAN PWM Control | ||
| F1SENSE | in | FAN Sense | ||
| DONE | in | FPGA DONE | ||
| IO1 | in | FPGA I2C SCL_t | ||
| IO2 | out | FPGA I2C SCL_i | ||
| IO3 | in | FPGA I2C SDA_t | ||
| IO4 | out | FPGA I2C SDA_i | ||
| IO5 | in | FPGA User LED control | ||
| SCL_R | out | SCL Strong Pull-Up Enable | ||
| SDA_R | out | SDA Strong Pull-Up Enable | ||
| SCL | inout | I2C SCL | ||
| SDA | inout | I2C SDA |
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