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Scroll Title
anchorTable_DRH
titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-10-252018.2TEF1001-test_board_noprebuilt-vivado_2018.2-build_03_20181024154054.zip
TEF1001-test_board-vivado_2018.2-build_03_20181024154034.zip		John Hartfiel
  • 2018.2
  • add TEF1001-02
  • MIG Configuration for AW12P7218BLK0M (4GB for REV01)
  • MIG Configuration for AW24P7228BLK0M (8GB for REV02)
  • BUGFIX QSPI IP configuration
  • add SREC to load application into DDR
2018-03-072017.4TEF1001-test_board_noprebuilt-vivado_2017.4-build_06_20180307102924.zip
TEF1001-test_board-vivado_2017.4-build_06_20180307102845.zip		John Hartfiel
  • 2017.4 update
  • new assembly variant
2017-11-282017.2TEF1001-test_board-vivado_2017.2-build_05_20171128114335.zip
TEF1001-test_board_noprebuilt-vivado_2017.2-build_05_20171128114350.zip		John Hartfiel
  • initial release

Release Notes and Know Issues

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Code Block
languageruby
title_i_io_ddr_clk.xdc

#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN AB11 [get_ports CLK_DDR3_200MHz_clk_p]
set_property PACKAGE_PIN AC11 [get_ports CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]

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