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Table 6: System Controller CPLD special purpose I/O pins.

Quad SPI Interface

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

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Figure 3: Power Distribution DiagramSee Xilinx data sheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.Diagramee

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