TE0745 TRM

Overview

The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.

Key Features

• Industrial/Commercial/Expanded grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)

  • 250 FPGA PL I/Os (120 LVDS pairs possible)
  • 17 PS MIOs on B2B connector available
  • Temperature Grade: Expanded (-40 to +100 °C)
• Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
• DDR3L SDRAM, 512MB or 1GB , 16 bit width address
• 32 or 64 MByte QSPI Flash memory
• 4 or 8 GTX transceiver lanes (XC7Z030 has 4) 
• Gigabit Ethernet transceiver PHY
• EEPROM for storing Ethernet MAC Address
• Hi-speed USB 2.0 ULPI transceiver with full OTG support
• Programmable quad clock generator
• Temperature compensated RTC (real-time clock)
• Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
• On-board high-efficiency DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• User LED
• Evenly-spread supply pins for good signal integrity
• Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0745-02 Block Diagram.

Main Components

Figure 2: TE0745-02 SoC module.

1. Xilinx Zynq XC7Z family SoC, U1
2. 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
3. Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
4. Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U7
6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
7. TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
8. Intersil ISL12020MIRZ Real-Time-Clock, U24
9. TI TCA9517 level-shifting I²C bus repeater, U17
10. Red LED, D2
    
11. Green LED, D1
12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit word width), U5
13. Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
    
14. TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
15. TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
16. TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
17. Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
22. 256 Mbit Quad SPI Flash memory (Micron N25Q256A), U14
23. Microchip USB3320 USB transceiver PHY , U32
24. Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
25. Microchip 24AA025E48 EEPROM for MAC address, U23
    
26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
    

Initial Delivery State

Table 1: Initial delivery state.

Signals, Interfaces and Pins

Board to Board (B2B) I/O's

The B2B connectors are high-speed hermaphroditic stacking strips providing modular interface to the SoC's PL and PS I/Os. Both single ended and differential signaling LVDS pairs are supported.

Table 2: Count, type and voltage range of SoC's PL and PS I/O banks pins available through B2B connectors.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin-out, please refer to the Pin-out Table.

The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pair, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: SoC's MGT lanes connections to the B2B connectors.

Below are listed MGT banks reference clock sources.

Table 4: MGT reference clock sources.

¹⁾ Note: MGT bank 111 not available at XC7Z030 Zynq SoC.

JTAG Interface

JTAG interface access is provided through the SoC's PS configuration bank 0 and is available on B2B connector J1.

Table 5: JTAG interface signals.

System Controller I/O's

Following special purpose pins are connected to System Controller CPLD:

Table 6: System Controller CPLD special purpose I/O pins.

Quad SPI Interface

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 7: MIO-pin assignment of the Quad SPI Flash memory IC.

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

Table 8: Ethernet PHY interface connections.

USB Interface

USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

Table 9: USB PHY interface connections.

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The I²C interface on B2B connector J2 has PS_3.3V as reference voltage and is connected to the Zynq SoC via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).:

Table 10: Pin assignment of the B2B I²C interface.

The on-module I²C interface works with reference voltage 1.8V:

Table 11: MIO-pin assignment of the on-module I²C interface.

Except the on-module RTC (U24), all other on-module I²C slave devices are operating with the reference voltage PS_1.8V.

I²C addresses for on-module devices are listed in the table below:

Table 12:  Module's I²C-interfaces overview.

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21 (permanent logic high in standard SC-CPLD firmware).The boot mode selection will be set by the Zynq's PS MIO pins MIO3...MIO5.

Following table describes how to set the control lines to configure the boot mode:

Table 13: Selectable boot modes.

In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. Basically MIO5 is set to 1 and JTAG is in cascade.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.

A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq module (master) and reference clock signal generator (slave).

Table 14: Programmable quad PLL clock generator inputs and outputs.

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 15: Clock sources overview.

On-board LEDs

Table 16: LEDs of the module.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 17: Typical power consumption. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.

It is important that all baseboard I/Os are tri-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.

Power Distribution Dependencies

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:

Figure 3: Power Distribution Diagramee

Power-On Sequence Diagram

The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Figure 4: Power-On Sequence

The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.

Voltage Monitor Circuit

The voltages 'VCCPINT' and 'PS_1.8V' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (available on J2-131 or SC-CPLD) to GND. Leave this pin unconnected or connect to VDD (PS_1.8V) when unused.

Figure 5: Voltage monitor circuit.

Power Rails

Table 18: Power rails of the SoC module on B2B connectors.

Bank Voltages

Table 19: Range of SoC module's bank voltages.

B2B connectors

Variants Currently In Production

Table 20: Module variants.

Technical Specification

Absolute Maximum Ratings

Table 21: Module absolute maximum ratings.

Recommended Operating Conditions

Table 22: Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Figure 6: Physical dimensions of the TE0745 SoC module.

Revision History

Hardware Revision History

Table 23: Module hardware revision history.

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Figure 7: TE0745 module revision number.

Document Change History 

 V.79

Table 24: Document change history.

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