Page History

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Click Finish in the bottom left to close the window - Arria V/Cyclone V Hard Processor System - hps_0 .
To change or correct these parameters later click onto the IP cores top entry in the list in the
tab System Contents - Column Name - hps_0.

Add Connections via clicking into the circle marked with a red rectangle in th picture above.
hps_0 - h2f_reset     →          clk_0 - clk_in_reset
clk_0 - clk                 →          hps_0 - f2h_sdram0_data

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Hit for good measure:
System  →  Assign Base Addresses
System  →  Assign Interrupt Numbers
System  →  Assign Custom Instruction Opcodes
System  →  Create Global Reset Network

UNKLAR!!!!------------------------------------

The Hardware Description language file is obtained by pressing Generate HDL in the bottom right corner of the
window.

A new window opens, forcing to save the design. Name the file, the guide designates the file
PlatformEditorHPS.qsys .

A new window opens, - Generation . In this window under Synthesis, selectvia Dropdown Menu in which
Hardware Language your HDL will be created, Verilog or VHDL, and check Create block symbole file (.bsf) .

Bottom right corner  →  Hit Generate HDL test
A new window opens, forcing to save the design. Give the file a name e.g. PlatformEditorHPS.qsys .
New window opens, under Synthesis, select which Hardware Language you prever Verilog ↔ VHDL
( Check - Create block symbole file (.bsf)
Click Generate and wait → Must be "Save System: completed successfully"

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Hit Finish, Plattform Editor window closes

UNKLAR!!!!------------------------------------ENDE

FRAGE: Enable MPU Interrupts auswählen, dann muss das verbunden werden oder Exportiert, wohin / womit?

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