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Before Generating HDL
System → Assign Base Addresses
System → Assign Interrupt Numbers
System → Assign Custom Instruction Opcodes
System → Create Global Reset Network
UNKLAR!!!!------------------------------------
Klarheit
Press Generate HDL → Setup of window Generation → Generate
→ Window opens for saving press Save → Name the save and press save
Saving window opens → press close - Message: Save System: Completed successfully
Another window opens - Generate → press close - Message: Generate: completed with warnings
Close Plattform Designer by pressing Finish
Klarheit end
The Hardware Description language file is obtained by pressing Generate HDL in the bottom right corner of the
window.
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A new window opens, - Generation . In this window under Synthesis, selectvia Dropdown Menu in which
Hardware Language your HDL will be created, Verilog or VHDL, and check Create block symbole file (.bsf) .
Press Generate HDL → Setup of window Generation → Generate
→ Window opens for saving press Save → Name the save and press save
Saving window opens → press close - Message: Save System: Completed successfully
Another window opens - Generate → press close - Message: Generate: completed with warnings
Close Plattform Designer by pressing Finish
Löschen!!!!------------------------------------
Bottom right corner → Hit Generate HDL test
A new window opens, forcing to save the design. Give the file a name e.g. PlatformEditorHPS.qsys .
New window opens, under Synthesis, select which Hardware Language you prever Verilog ↔ VHDL
( Check - Create block symbole file (.bsf)
Click Generate and wait → Must be "Save System: completed successfully"
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Hit Finish, Plattform Editor window closes
UNKLARLöschen!!!!------------------------------------ENDE
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