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Achtung beim Schritt HDL generate - Stimmt meine beschreibung mit den Fenstern überein?
The Hardware Description language file is obtained by pressing Generate HDL in the bottom right corner of the
window.
A new window opens, - Generation. In this window, under Synthesis, select via Dropdown Menu in which
Hardware Language your HDL will be created, Verilog or VHDL, check Create block symbole file (.bsf) and
uncheck Create timing and resource estimate... .
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