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This step guides through the tasks which have to be done inside the Intel SoC Embedded Development Suite. As mentioned in page "Board bring-up overview for TEI0022" this step is for preloader and bootloader generation which should be done in the following next three steps:
- Preparation
- Preloader/Bootloader Generation
- Device Tree Generation
The section "Preparation" describes preparing steps which are necessary for the generation of the preloader and the bootloader which is described in section "Preloader/Bootloader Generation". After that in section "Device Tree Generation" the steps to create the device tree blob is explained.
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Requirements - EIGENTLICH ÜBERFLÜSSIG, da auf Seite 0 geschrieben... . ?!?
All steps to format / setup a bootable SD card can only be performed within a Linux,
(Windows Subsystem for Linux is not capable to format a SD card) the Linux tool fdisk / sfdisk depend on it.
The tools bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.
An installation of INTEL SoC FPGA EMBEDDED DEVELOPMENT SUITE along with Intel Quartus Prime Lite, so the tools
bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.
Background
The boot process of the HPS consists of several stages:
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Preparation
After compilation of the While Intel Quartus project compilation, described on page Intel Quartus Project, the folder "hps_isw_handoff" is existing inside the project folder. Therefore, if this folder does not exist fix the issue and return to this point.
BSP Editor
The BSP-Editor takes the handoff folder and generates further source and configuration files to be able to compile
the U-Boot Preloader and U-Boot Bootloader for the HPS.
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is created which is now needed to generate via the bsp-editor further output for preloader and bootloader generation. To do the preparation follow the following guide:
- Start the SoC EDS Shell as administrator. To do that navigate to C:\intelFPGA\18.1\embedded\
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- , right click on the file "Embedded_Command_Shell.
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- bat", and select "Run as administrator
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- ". Click Yes in the
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- window
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- "User Account Control".
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- In the opened shell start the bsp-editor via: bsp-editor.exe
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- In the opened bsp-editor select File → New HPS BSP...
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- In the opened New BSP
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- dialogue click onto
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- ... and select the PlatformEditorHPS_hps_0 folder inside
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- the hps_isw_handoff folder
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- .
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Back in the BSP-Editor, the U-Boot preloader must be configured. In the right column, under spl.boot are four Checkboxes,
each beginning with BOOT_FROM_... check only BOOT_FROM_SDMMC , the following three lines are of no interest.
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- After that, click Open in this dialogue and OK in the previous dialogue.
- Now, in the bsp-editor, the preloader should be configured. Select only BOOT_FROM_SDMMC as BOOT_FROM_-parameter in the right window under the spl.boot header.
- Select FAT_SUPPORT.
- Select 1 as FAT_BOOT_PARTITION.
- Select u-boot.img as FAT_LOAD_PAYLOAD_NAME
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- Then, generate the output via clicking the Generate button.
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- After generation, an information like
- Finished generation BSP files. Total time taken =
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- ... seconds is
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- displayed in the information tab. The folder software should now be available.
- Close the bsp-editor.
Preloader/Bootloader Generation
After this preparation, it is possible to generate the preloader and the bootloader inside the shell while following the guide:
In your project folder, the folder - software - appears.
U-Boot - Make preloader and main bootloader
The handoff folder contains now after the previous steps all the sources to compile the booot loaders.
On Windows 10 - Version 1909 - and cygwin - Version 2.0 - all commands which require decompressing of source archives, have to be
pointed into the right folder to be executed from, these commands beginn with /usr/bin/ . All commands are in italic and bold,
comments to commands are in brackets.
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- Change into folder .../software/spl_bsp inside the project folder with the change directory command cd. For example:
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- cd Project/software/spl_bsp
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- Clean the folder via running /usr/bin/make clean
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- Configure the build process via
- /usr/bin/make
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- config which generates
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- the folder .../software/spl_bsp
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- /uboot-socfpga.
- Generate the preloader via /usr/bin/make which generates the file .../software/spl_bsp/preloader-mkpimage.bin
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- .
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- Generate the bootloader via /usr/bin/
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- make uboot which generates the image .../software/spl_bsp
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- /uboot-socfpga/u-boot.img.
After that, the folder .../software/spl_bsp/ should look like the following figure.
The folder .../software into softwae/spl_bsp/uboot-socfpga )
should contain the files shown in the next figure.
Device Tree
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Lastly, the Device Tree Blob must be generated, whereby Linux can start automated without user interaction.
It acts as an Interface from the board hardware to the Linux Kernel. The .dtb file informs the Linux Kernel about the existing Hardware,
its Configuration and which driver to use for controlling it.
Generate - .dtb or .dts file from .sopcinfo file
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Generation
The device tree generation is a crucial part to tell the linux kernel which hardware has to be handled. To generate the device tree blob follow this guide:
- For device tree generation the Golden Hardware Reference Design file .../intelFPGA/18.1/embedded/examples/hardware/cv_soc_devkit_ghrd
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- /hps_common_board_info.xml is needed. Therefore, copy this file into the project folder where the software folder, the output_files folder, ... are. This file contains information regarding the board which can be adapted, if necessary.
- Generate the device tree via the shell command: sopc2dts --input <Project Name>.sopcinfo --output socfpga.dtb --type dtb --board hps_common_board_info.xml --bridge-removal all --clocks
- The output in the following listing can be ignored.
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$ sopc2dts.exe --input PlatformEditorHPS.sopcinfo --output DTBsocfpga.dts --type dts --board hps_common_board_info.xml --bridge-removal all --clocks
MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null
MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null
DTAppend: Unable to find parent, null, for #address-cells. Adding to root
DTAppend: Unable to find parent, null, for #size-cells. Adding to root
DTAppend: Unable to find parent, null, for reg. Adding to root
DTAppend: Unable to find parent, null, for spi-max-frequency. Adding to root
DTAppend: Unable to find parent, null, for m25p,fast-read. Adding to root
DTAppend: Unable to find parent, null, for page-size. Adding to root
DTAppend: Unable to find parent, null, for block-size. Adding to root
DTAppend: Unable to find parent, null, for tshsl-ns. Adding to root
DTAppend: Unable to find parent, null, for tsd2d-ns. Adding to root
DTAppend: Unable to find parent, null, for tchsh-ns. Adding to root
DTAppend: Unable to find parent, null, for tslch-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,page-size. Adding to root
DTAppend: Unable to find parent, null, for cdns,block-size. Adding to root
DTAppend: Unable to find parent, null, for cdns,read-delay. Adding to root
DTAppend: Unable to find parent, null, for cdns,tshsl-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,tsd2d-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,tchsh-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,tslch-ns. Adding to root |
Device Tree Blob
Generate - .dtb or .dts file from .sopcinfo file
To generate the .dtb file, a folder containing the Golden Hardware Reference Design for Cyclone 5 FPGA's is required. A copy of it is
part of Intels SoC FPGA Embedded Development Suite. To be on the safe side, copy the file
soc_system_18_1_09132018_94307.tar.gz
inside the folder
c:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\tgz\
to new folder inside your project directory, for example,
c:\Project\ghrd_cyc5
via a file browser.
Use a SoC EDS SHell with administrative privileges to navigate to your newly folder
cd c:/Project/ghrd_cyc5
and extract the .tar.gz archieve .
tar xvf soc_system_18_1_09132018_94307.tar.gz (Decompress the archieve)
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Enter into the Shell the following command:
sopc2dts --input HPS.sopcinfo --output DTBsocfpga.dtb --type dtb --board hps_common_board_info.xml --bridge-removal all --clocks
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dtc -I dtb -O dts -o devicetree.dts soc_system.dtb
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Informationsfragmente:
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Requirements - EIGENTLICH ÜBERFLÜSSIG, da auf Seite 0 geschrieben... . ?!?
All steps to format / setup a bootable SD card can only be performed within a Linux,
(Windows Subsystem for Linux is not capable to format a SD card) the Linux tool fdisk / sfdisk depend on it.
The tools bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.
An installation of INTEL SoC FPGA EMBEDDED DEVELOPMENT SUITE along with Intel Quartus Prime Lite, so the tools
bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.
Background
The boot process of the HPS consists of several stages:
- Boot ROM
- Hard coded into the chip
- It's purpose is to detect the selected boot source
- Perform minimal Setup of the HPS
- Load the next Boot stage [Preloader / u-boot-spl] into the On chip RAM [OCRAM]
therefore the preloader / SPL u-boot is limited to 64 kByte on Cyclone 5 devices - Preloader
- Perform additional HPS initialization
- Bring up SDRAM
- Load the next boot stage from Flash to SDRAM and jump to it
- Preloader-optins:
u-boot - SPL
SoC EDS - MPL [Altera bare-metal libraries - HWLibs]
- For Cyclone 5 devices, the preloader consists of 4 identical copies. each 64 kB in size,
256 kb in total
- When generating the preloader, it can be necessary to manually add a header and checksum
into the binary, the tool mkpimage can perform these additions - Main Bootloader
- Load Linux [u-boot] or Bare Metal Application into the RAM
- Jump to it.
In case of Linux, load Kernel, followed by the loading of the Linux rootfs
- When generating the preloader, it can be necessary to manually add a header and checksum
into the binary, the tool mkimage can perform these additions
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