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Template Revision 1.8 9 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Overview

Firmware for system controller TEI0022 Intel MAX 10 with designator U41: 10M08SAU169C8G

Feature Summary

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Fan Controlcontrol
FMC Voltage Control
JTAG Controlcontrol
LED Controlcontrol
UART
User Button
Power Management
button
Power management
Power regulator mode control
FMC Power control
Reset management
Configuration sheme controlReset Management

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

JTAGSEL0 / JTAGSEL0F9_MAX10JTAGSEL1 / JTAGSEL1E9_MAX10G2_MAX10F6_MAX10FTDI_JTAG_TMS/CS / FTDI_TMSG1 JTAG TCKJ6J1M10FTDI_JTAG_TDI/DO / FTDI_TDOF5HPS_TCK / HPS_TCKK1HPS_TDI / HPS_TDIM4HPS_TMS / HPS_TMSM7HPS JTAG TMS_TCK / FPGA_TCKK2 JTAG TCKFPGA_TDO / FPGA_TDIL2FPGA_TMS / FPGA_TMSJ2M8 JTAG TCKFMCTDI / TDIM9FMC_TMS / FMC_TMSM11J5Reset ButtonHPSRST#_BO / HPS_RSTn_BOK6HPS_WARM_RST#_SW / HPS_WARM_RSTn_SWK5C1 UART TXDCPUGPIO_4 / CPU_GPIO4H4D13MODE_VCC / MODE_DCDC_VCCD9_MAX10MODE / MODE_DCDC_5VA11_MAX10E10_MAX10MODE_DDR_HPS / MODE_DCDC_HPSF10_MAX10 DDR Power DCDC Mode SelectionA8_MAX10PG_VCC / PG_VCCB11_MAX10PG_+2.5V / PG_2V5C11_MAX102.5 V Power GoodPG_+1.8V / PG_1V8D11_MAX10B12A10EN_+2.5V / EN_2V5A122.5 V Power EnableEN_+1.8V / EN_1V8D12+1.8 V Power Enable / LED_VCC Power LedEN_+3.3V / EN_3V3B13EN_+0.9V / EN_0V9F1+0.9 V Power Enable+1.8 V / LED_1V8H2EN_DDR_HPS / ENF13 Power EnableEN_DDR_FPGA / EN_DDR_FPGAE13J7C12EN_FMC / EN_FMCE1C10_MAX10C13_MAX10FMC_PG_C2M / FMC_PG_C2MK7POK_FMC / POK_FMCE3Power Good for FMC Voltage at U43VDD_FPGA / PG_VDD_FPGAE12FPGA VDD DDR Power GoodVDD_HPS / PG_VDD_HPSG10C9E6D6 DDR VTT Power Good LedLEDDDR_ / LED_VDD_DDR_HPSH3 DDR VDD Power Good LedLEDDDR_HPS / LED_VTT_DDRoutG4 DDR VTT Power Good LedJTAGEN /E5EN_+5.0V / EN_5V0A7B10B9A6B6A4MAX10A3C4CONF_DONE /C5 /BDBUS6 /A5CLK_MAX10 /H6ETH_RST /G5H5M2M1N3N2L3J9H10FPGAJ13H9H8G13N4N6N8N7M12M13K8J8N12

Name / opt. VHD Name	Direction	Pin	Bank Power	Description
BOOTSEL2 / BOOTSEL2	out	L10	+3.3V	Boot Select Bit 2	HPS boot select pin 2
CPU_GPIO_0	in	N10	+3.3V	Select JTAG Connection		Voltage selection via software for FMC_VADJ (U43 → VS0 pin)
CPU_GPIO_1		in	N9	+3.3V	Select JTAG Connection	FTDI_JTAG_TC/SK / FTDI_TCK	in		Voltage selection via software for FMC_VADJ (U43 → VS1 pin)
CPU_GPIO_2	in	N11		+3.3V	FTDI JTAG TCK	FTDI_JTAG_TDO/DI / FTDI_TDI	in		Voltage selection via software for FMC_VADJ (U43 → VS2 pin)
CPU_GPIO_3	in	L1	+3.3V	FMC power enable control via software
CPU_GPIO_4	in	H4		+3.3V	FTDI JTAG TDI		Fan control via software
BDBUS0	in	D1	+3.3V_MAX10	FTDI	HPS_TDO / HPS_TDO	in	UART TXD pin
BDBUS1	out	C1		+3.3V	HPS JTAG TDO	FPGA_TDI / FPGA_TDO	in	_MAX10	FTDI UART RXD pin
EN_0V9	out	F1		+3.3V	FPGA JTAG TDO	FMC_TDO / FMC_TDO	in	_MAX10	+0.9V power enable
EN_1V8	out	D12		+3.3V	FMC JTAG TDO	_MAX10	+1.8V power enable
EN_2V5	out	A12	+3.3V_MAX10	FTDI JTAG TDO	+2.5V power enable
EN_3V3		out	B13	+3.3V	HPS JTAG TCK	_MAX10	+3.3V power enable
EN_5V0	out	A7	+3.3V	HPS JTAG TDI	_MAX10	+5.0V power enable
EN_DDR_FPGA	out	E13	+3.3V	_MAX10	FPGA	DDR power enable
EN_DDR_HPS	out	F13	+3.3V_MAX10	HPS	DDR power enable
EN_FMC		out	E1	+3.3V	FPGA JTAG TDI	_MAX10	FMC_VADJ power enable
EN_FMC_3V3	out	C13	+3.3V	FPGA JTAG TMS	FMC_TCK/ FMC_TCK	out	_MAX10	+3.3V	FMC	power enable
EN_	FMC_	12V	out	C12	+3.3V_MAX10	FMC JTAG TDI	+12.0V FMC power enable
EN_VCC	out	A10	+3.3V	FMC JTAG TMS	HPS_RST#_SW / HPS_RSTn_SW	in	_MAX10	VCC power enable
FAN_EN	out	D13		+3.3V_MAX10	Fan control
FMC_	PG_C2M	out	K7	in		+3.3V	Brown Out Detection	FMC power good signal to FMC connector
FMC_PRSNT_M2Cn	in	J7	+3.3V	Warm Reset Button
FPGA_RST#_SW / FPGA_RSTn_SW	in	B4	+3.3V_MAX10	FPGA Reset Button
HPS_RST# / HPS_RSTn	out	L11	+3.3V	HPS Reset
HPS_WARM_RST# / HPS_WARM_RSTn	out	M3	+3.3V	HPS Warm Reset
FPGA_RST# / FPGA_RSTn	out	L13	VDD_DDR_FPGA	FPGA Reset
VID0_SW / VID0_SW	in	F8	+3.3V_MAX10	Power Selection Pin 0 for FMC Voltage
VID1_SW / VID1_SW	in	E8	+3.3V_MAX10	Power Selection Pin 1 for FMC Voltage
VID2_SW / VID2_SW	in	D8	+3.3V_MAX10	Power Selection Pin 2 for FMC Voltage
CPU_GPIO_0 / CPU_GPIO0	in	N10	+3.3V	CPU GPIO 0 (used for automatic power selection for FMC Voltage)
CPU_GPIO_1 / CPU_GPIO1	in	N9	+3.3V	CPU GPIO 1 (used for automatic power selection for FMC Voltage)
CPU_GPIO_2 / CPU_GPIO2	in	N11	+3.3V	CPU GPIO 2 (used for automatic power selection for FMC Voltage)
VID0 / VID0	out	B2	+3.3V_MAX10	Power Selection Pin 0 for FMC Voltage at U43
VID1 / VID1	out	C2	+3.3V_MAX10	Power Selection Pin 1 for FMC Voltage at U43
VID2 / VID2	out	F4	+3.3V_MAX10	Power Selection Pin 2 for FMC Voltage at U43
PWR_SEL / PWR_SEL	out	E4	+3.3V_MAX10	Power Selection for Cyclone V FMC VCCPD at U37
USER_BTN_SW / USER_BTN_SW	in	B3	+3.3V_MAX10	User Button
USER_BTN_FPGA / USER_BTN_FPGA	out	G12	VDD_DDR_FPGA	FPGA User Button
BDBUS0 / FTDI_RXD	in	D1	+3.3V_MAX10	FTDI UART RXD
FPGA_GPIO_1 / FPGA_IO1	in	J10	VDD_DDR_FPGA	FPGA IO 1
FPGA_GPIO_0 / FPGA_IO0	out	K11	VDD_DDR_FPGA	FPGA IO 0
FMC card detection from FMC connector / currently_not_used
FPGA_GPIO_0	out	K11	VDD_DDR_FPGA	FPGA IO (FPGA pin AG10) / FPGA UART RXD
FPGA_GPIO_1	in	J10	VDD_DDR_FPGA	FPGA IO (FPGA pin AH9) / FPGA UART TXD
FPGA_RSTn	out	L13	VDD_DDR_FPGA	FPGA reset
FPGA_RSTn_SW	in	B4	+3.3V_MAX10	FPGA reset button
FMC_TCK	out	M8	+3.3V	FMC JTAG TCK
FMC_TDI	out	M9	+3.3V	FMC JTAG TDI
FMC_TDO	in	M10	+3.3V	FMC JTAG TDO
FMC_TMS	out	M11	+3.3V	FMC JTAG TMS
FPGA_TCK	out	K2	+3.3V	HPS JTAG TCK
FPGA_TDI	out	J1	+3.3V	FPGA JTAG TDI
FPGA_TDO	in	L2	+3.3V	FPGA JTAG TDO
FPGA_TMS	out	J2	+3.3V	FPGA JTAG TMS
FTDI_JTAG_TCK	in	G2	+3.3V_MAX10	FTDI JTAG TCK
FTDI_JTAG_TDI	in	F5	BDBUS1 / FTDI_TXD	out		+3.3V_MAX10	FTDI	JTAG TDI
FTDI_	in	JTAG_TDO	out	F6	+3.3V	CPU GPIO 4 (used for fan control)	FAN_EN / FAN_EN	out	_MAX10	FTDI JTAG TDO
FTDI_JTAG_TMS	in	G1		+3.3V_MAX10	Fan Control	FTDI JTAG TMS
HPS_TCK	out	K1	+3.3V	VCC DCDC Mode Selection		HPS JTAG TCK
HPS_TDI	out	M4	+3.3V	+5.0 V DCDC Mode Selection	MODE_DDR_FPGA / MODE_DCDC_FPGA	out		HPS JTAG TDI
HPS_TDO	in	J6		+3.3V	FPGA DDR Power DCDC Mode Selection		HPS JTAG TDO
HPS_TMS	out	M7	+3.3V		HPS	JTAG TMS
HPS_RSTn	out	L11	PG_+5.0V / PG_5V0	in		+3.3V	+5.0 V Power Good		HPS reset
HPS_RSTn_BO	in	K6	+3.3V	VCC Power Good		Brown Out detection
HPS_RSTn_SW	in	J5	+3.3V		Reset button
HPS_WARM_RSTn	out	M3		+	3.3V	HPS warm reset
HPS_WARM_RSTn_SW		in	K5	+3.3V	HPS warm reset button
JTAGSEL0	+1.8 V Power Good	PG_+3.3V / PG_3V3	in	F9	+3.3V_MAX10	+3.3 V Power Good	EN_VCC / EN_VCC	out	Select JTAG connection
JTAGSEL1	in	E9		+3.3V_MAX10	VCC Power Enable	Select JTAG connection
LED_1V8		out	H2	+3.3V_MAX10	+	1.8V power led
LED_FMC_VADJ		out	C9	+3.3V_MAX10	FMC_VADJ power good led
LED_VCC		out	F12	+3.3V_MAX10	VCC	power good led
LED_VDD_DDR_FPGA		out	E6	+3.3V_MAX10	+3.3 V Power Enable	FPGA DDR VDD power good led
LED_VDD_DDR_HPS	out	H3	+3.3V_MAX10	HPS DDR VDD power good led
LED_	VTT_DDR_FPGA	out	D6	+3.3V_MAX10	+1.8 V Power Led	FPGA DDR VTT power good led
LED_VTT	_DDR_HPS	out	G4	+3.3V_MAX10	HPS DDR	VTT power good led
MODE	out	A11	+3.3V_MAX10	FPGA DDR Power Enable
CPU_GPIO_3 / CPU_GPIO3	in	L1	+3.3V	CPU GPIO 3 (used for FMC Power Enable)
+5.0V voltage regulator mode selection
MODE_DDR_FPGA	out	E10	FMC_PRSNT_M2C# / FMC_PRSNT_M2Cn	in		+3.3V	FMC Card Detection from FMC Connector	EN_FMC_+12.0V / EN_FMC_12V	out	_MAX10	Voltage regulator mode selection for FPGA DDR power
MODE_DDR_HPS	out	F10		+3.3V_MAX10	+12.0 V FMC Power Enable	Voltage regulator mode selection for HPS DDR power
MODE_VCC	out	D9	+3.3V_MAX10	Power Enable for FMC Voltage at U43	PWR_SWT_EN / PWR_VCCPD_EN	out		VCC voltage regulator mode selection
MSEL0	out	N5	+3.3V	Configuration mode selection pin 0
MSEL1	out	N3		+3.3V	Power Enable for Cyclone V VCCPD Voltage	EN_FMC_+3.3V / EN_FMC_3V3	out		Configuration mode selection pin 1
MSEL2	out	N2	+3.3V	Configuration mode selection pin 2
MSEL3	out	N4		+3.3V	+3.3 V FMC Power Enable		Configuration mode selection pin 3
MSEL4	out	N6	+3.3V	FMC Power Good Signal to FMC Connector	Configuration mode selection pin 4
PG_1V8		in	D11	+3.3V_MAX10	+1.8V power good signal
PG_	2V5	in	C11	+3.3V_MAX10	+2.5V power good signal
PG_	3V3	in	B12	+3.3V_MAX10	HPS VDD DDR Power Good	LED_FMC_VADJ / LED_FMC_VADJ	out	+3.3V power good signal
PG_5V0	in	A8		+3.3V_MAX10	Power Good Led for FMC Voltage at U43	LED_VDD_DDR_FPGA / LED_VDD_DDR_FPGA	out	+5.0V power good signal
PG_VCC	in	B11		+3.3V_MAX10	FPGA DDR VDD Power Good Led	LED_VTT_DDR_FPGA / LED_VTT_DDR_FPGA	out	VCC power good signal
PG_VDD_FPGA	in	E12		+3.3V_MAX10	FPGA	VDD DDR power good signal
PG	_VDD_	HPS	out		in	G10	+3.3V_MAX10	HPS	VDD DDR power good signal
PG	_VTT_FPGA	in	B10	+3.3V_MAX10	FPGA VTT DDR power good signal
PG_VTT	_HPS	in	B5	+3.3V_MAX10	HPS	VTT DDR power good signal
POK_FMC	in	E3	+3.3V_MAX10	Select JTAG Connection	FMC_VADJ power good signal
PWR_SEL	out	E4	+3.3V_MAX10	+5.0 V Power Enable	PG_VTT_FPGA / PG_VTT_FPGA	in	Power selection pin for FMC_VCCPD voltage at U37 (Cyclone V - Bank 8A VCCPD voltage)
PWR_SWT_EN	out	C10		+3.3V_MAX10	FPGA VTT DDR Power Good
PG_VTT_HPS / PG_VTT_HPS	in/out	B5	+3.3V_MAX10	HPS VTT DDR Power Good
STATUS /	-	H1	+3.3V_MAX10	/ currently_not_used
Power enable pin for FMC_VCCPD voltage at U37
USER_BTN_FPGA	out	G12	VDD_DDR_FPGA	FPGA user button pin
USER_BTN_SW	in	B3	BDBUS2 /	-	B1	+3.3V_MAX10	/ currently_not_used	BCBUS2 /	-	A9	user button
VID0_SW	in	F8	+3.3V_MAX10	/ currently_not_used	DEVCLRn /	-	Dip switch S8A for FMC_VADJ voltage selection
VID1_SW	in	E8		+3.3V_MAX10	/ currently_not_used	BDBUS7 /	-	Dip switch S8B for FMC_VADJ voltage selection
VID2_SW	in	D8		+3.3V_MAX10	/ currently_not_used	BCBUS1 /	-	Dip switch S8C for FMC_VADJ voltage selection
VID0	out	B2		+3.3V_MAX10	/ currently_not_used	BDBUS5 /	-	Voltage selection pin 0 (VS0) for FMC_VADJ voltage at U43
VID1	out	C2		+3.3V_	/ currently_not_used	BDBUS4 /	-	MAX10	Voltage selection pin 1 (VS0) for FMC_VADJ voltage at U43
VID2	out	F4		+3.3V_MAX10	/ currently_not_used	nSTATUS /	-	Voltage selection pin 2 (VS0) for FMC_VADJ voltage at U43
JTAGEN	in	E5		+3.3V_MAX10	/ currently_not_used	enable/disable JTAG access to system controller MAX10
BDBUS2		-	B1	+3.3V_MAX10	/ currently_not_used
BDBUS3		-	A2	+3.3V_MAX10	/ currently_not_used
BDBUS4	-	A3	+3.3V_MAX10	/ currently_not_used
BDBUS5	-	A4	+3.3V_MAX10	/ currently_not_used
BDBUS6	-	A5	+3.3V_MAX10	/ currently_not_usedUSB
_RSTBDBUS7	-	A6	+3.3V_MAX10	/ currently_not_usedUSER_BTN_HPS
/CLK_MAX10	-	H6	+3.3V	SI5338A → CLK2A pin / currently_not_used
nCONFIG_I /CLKSEL0	-	N8	+3.3V	/ currently_not_usedMSEL1 /
CLKSEL1	-	N7	+3.3V	/ currently_not_usedMSEL2 /
CONF_DONE_I	-	L5	+3.3V	Cyclone V CONF_DONE pin / currently_not_usedUSB
_HUB_RST /DEVCLRn	-	B9	+3.3V_MAX10	Device-wide reset for MAX 10 / currently_not_used
FPGA_GPIO_9 /ETH_RST	-	K10	VDD_DDR_FPGA	G5	+3.3V	Ethernet phy reset / currently_not_usedFPGA_
GPIO_3 /FMC_SCL	-	L12	VDD_DDR_FPGA	N12	+3.3V	FMC I²C interface / currently_not_usedFPGA_
GPIO_2 /FMC_SDA	-	K12	VDD_DDR_FPGA	M13	+3.3V	FMC I²C interface / currently_not_usedFPGA_
GPIO_11 /FMC_TRST#	-	J12	VDD_DDR_FPGA	M12	+3.3V	FMC JTAG test reset / currently_not_used
FPGA_GPIO_8 /2	-	K12	VDD_DDR_FPGA	FPGA IO (FPGA pin AF11) / currently_not_used
FPGA_GPIO_12 /3	-	L12	VDD_DDR_	FPGA	FPGA IO (FPGA pin AG11) / currently_not_used
FPGA_GPIO_10 /4	-	G13	VDD_DDR_FPGA	FPGA IO (FPGA pin AA13) / currently_not_used
FPGA_GPIO_5 /	-	H13	VDD_DDR_FPGA	FPGA IO (FPGA pin AB13) / currently_not_used
FPGA_GPIO_7 /6	-	H8	VDD_DDR_FPGA	FPGA IO (FPGA pin AK2) / currently_not_used
FPGA_GPIO_6 /7	-	H9	VDD_DDR_FPGA	FPGA IO (FPGA pin AK3) / currently_not_used
FPGA_GPIO_4 /8	-	J9	VDD_DDR_FPGA	FPGA IO (FPGA pin AJ4) / currently_not_used
nSTATUS_I /FPGA_GPIO_9	-	L4	+3.3V	K10	VDD_DDR_FPGA	FPGA IO (FPGA pin AK4) / currently_not_used
CONFFPGA_DONEGPIO_I /10	-	L5	+3.3V	J13	VDD_DDR_FPGA	FPGA IO (FPGA pin AE13) / currently_not_used
HPS_TRST# /FPGA_GPIO_11	-	M5	+3.3V	J12	VDD_DDR_FPGA	FPGA IO (FPGA pin AF13) / currently_not_usedMSEL0 /
FPGA_GPIO_12	-	N5	+3.3V	H10	VDD_DDR_FPGA	FPGA IO (FPGA pin AD14) / currently_not_used
MSEL3 HPS_SPI_SS/BOOTSEL0	-	K8	+3.3V	HPS boot select pin 0 / currently_not_usedMSEL4 /
HPS_TRST#	-	M5	+3.3V	HPS JTAG test reset / currently_not_usedCLKSEL0 /
nCONFIG_I	-	M1	+3.3V	Cyclone V nCONFIG pin / currently_not_usedCLKSEL1 /
nSTATUS_I	-	L4	+3.3V	Cyclone V nSTATUS pin/ currently_not_used
FMCQSPI_TRST# CS/BOOTSEL1	-	J8	+3.3V	HPS boot select pin 1 / currently_not_used
FMC_SDA /STATUS	-	H1	+3.3V_MAX10	status led / currently_not_used
HPSUSB_SPIHUB_SS/BOOTSEL0RST	-	L3	+3.3V	USB hub (U33) reset / currently_not_used
QSPIUSB_CS/BOOTSEL1RST	-	H5	+3.3V	USB phy (U8) reset / currently_not_used
FMC_SCL /USER_BTN_HPS	-	M2	+3.3V	/ currently_not_used

Functional Description

DCDC Mode Control

The mode signals are connected to "1".

Signal	State	Description
MODE_DCDC_VCC, MODE_DCDC_5V	1	Forced Continous Mode
MODE_DCDC_VCC, MODE_DCDC_5V	0	Discontinous Mode
MODE_DCDC_FPGA, MODE_DCDC_HPS	1	Pulse-Skipping Mode for VDD
MODE_DCDC_FPGA, MODE_DCDC_HPS	0	Forced Continous Mode for VDD

Fan Control

Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO4".

FMC Voltage Control

The power is enabled if signal "CPU_GPIO3" is set to "1" and there is an FMC card. Then, the +12.0 V level is enabled. After that, the adjustable voltage is enabled. Finally, the +3.3 V level is enabled. Then, the signal "FMC_PG_C2M" is asserted.

JTAG Control

The FTDI JTAG is connected to the Intel MAX10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.

JTAG_SEL0	JTAG_SEL1	JTAGEN	JTAG Connection
X	X	1 - (ON)	Intel MAX10
0 - (ON)	0 - (ON)	0 - (OFF)	Cyclone V HPS
0 - (ON)	1 - (OFF)	0 - (OFF)	Cyclone V FPGA
1 - (OFF)	0 - (ON)	0 - (OFF)	FMC

LED Control

The leds signals their power good status.

UART

The second channel of the JTAG FTDI interface delievers an UART connection to the Intel Cyclone V fabric.

User Button

The User Button is connected to the FPGA.

Power Management

The power sequencing is handled inside the system controller according to the next figure.

...

S8-C	S8-B	S8-A	Voltage	Setting
ON	ON	ON	3.3 V	Manual
ON	ON	OFF	2.5 V	Manual
ON	OFF	ON	1.8 V	Manual
ON	OFF	OFF	1.5 V	Manual
OFF	ON	ON	1.25 V	Manual
OFF	ON	OFF	1.2 V	Manual
OFF	OFF	ON	0.8 V	Manual
OFF	OFF	OFF	CPU-dependent	CPU

Reset Management

The reset buttons are connected via the system controller to the according reset locations. That means that, if the reset button S1 or the brown-out detection is asserted, the Cyclone V should be reseted. If the warm reset button S3 is asserted, the Cyclone V should be warm reseted. If the FPGA reset button S4 is asserted, the FPGA could be reseted.

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV01 to REV02

Changed pin connections
Changed JTAG connection
Changed reset connection
Changed FMC Vadj Voltage selection
Changed power sequencing

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

...

Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

Page info

	modified-user
	modified-user

Work in progress

2020-02-19

v.19

REV02

Page info

	created-user
	created-user

Initial release

All

Page info

	modified-users
	modified-users

Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

...

Trenz Electronic Documentation

Versions Compared

Old Version 7

New Version 8

Key

Table of contents

Overview

Feature Summary

Fan Controlcontrol
FMC Voltage Control
JTAG Controlcontrol
LED Controlcontrol
UART
User Button
Power Management
button
Power management
Power regulator mode control
FMC Power control
Reset management
Configuration sheme controlReset Management

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

DCDC Mode Control

Fan Control

FMC Voltage Control

JTAG Control

LED Control

UART

User Button

Power Management

Reset Management

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

Legal Notices

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 7

New Version 8

Key

Table of contents

Overview

Feature Summary

Fan ControlcontrolFMC Voltage ControlJTAG ControlcontrolLED ControlcontrolUARTUser ButtonPower ManagementbuttonPower managementPower regulator mode controlFMC Power controlReset managementConfiguration sheme controlReset Management

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

DCDC Mode Control

Fan Control

FMC Voltage Control

JTAG Control

LED Control

UART

User Button

Power Management

Reset Management

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

Legal Notices

Fan Controlcontrol
FMC Voltage Control
JTAG Controlcontrol
LED Controlcontrol
UART
User Button
Power Management
button
Power management
Power regulator mode control
FMC Power control
Reset management
Configuration sheme controlReset Management