Versions Compared

Old Version 17

changes.mady.by.user Oleksandr Kiyenko

Saved on

compared with

New Version 18

changes.mady.by.user Oleksandr Kiyenko

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Name / opt. VHD NameDirectionPinBank PowerDescription
ADBUS0        inG93V_DFTDI TCK
ADBUS1        inF103V_DFTDI TDI
ADBUS2        outE103V_DFTDI TDO
ADBUS3        inD93V_DFTDI TMS
AVDD_SHDN     -inoutG103V_DAVDD Shutdown / AVDD OV/UV
BCBUS0        -D123V_D
BCBUS1        -E133V_D
BCBUS2        -E123V_D
BCBUS3        -F133V_D
BCBUS4        -F123V_D
BDBUS0        -B113V_D
BDBUS1        -A123V_D
BDBUS2        -B123V_D
BDBUS3        -C113V_D
BDBUS4        -B133V_D
BDBUS5        -C123V_D
BDBUS6        -C133V_D
BDBUS7        -D113V_D
CONF_DONE     -C53V_D
DET_BPR       -H23V_D
DET_RIO       -H33V_D
DONE          inN3PS_1V8FPGA Done
EN_3V3        outC103V_D3.3V Power Enable
EN_DAC1       outE63V_DDAC1 Power Enable
EN_DAC2       outE83V_DDAC2 Power Enable
EN_DAC3       outB63V_DDAC3 Power Enable
EN_DAC4       outA63V_DDAC4 Power Enable
EN_DDR        outG133V_DDDR Power Enable
EN_FPD        outL123V_DFPD Power Enable
EN_LPD        outJ133V_DLPD Power Enable
EN_PSGT       outB93V_DPSGT Power Enable
ERR_OUT       -G5PS_1V8
ERR_STATUS    -H6PS_1V8
F_TCK         outN2PS_1V8FPGA TCK
F_TDI         outM1PS_1V8FPGA TDI
F_TDO         inK1PS_1V8FPGA TDO
F_TMS         outJ1PS_1V8FPGA TMS
F1PWM         outH103V_DFAN PWM Control
F1SENSE       inJ93V_DFAN Sense
FTDI_RST      outE93V_DFTDI Reset
GA0           -F83V_D
GA0_R         -F93V_D
GA1           -A23V_D
GA1_R         -B23V_D
GA2           -A33V_D
GA2_R         -B33V_D
GA3           -A43V_D
GA3_R         -B43V_D
IEEE_SW_NC    -C93V_D
IEEE_SW_NO    -A113V_D
INIT_B        inL2PS_1V8FPGA Init
JTAGEN        -E53V_D
LED_FP_4      outM43.3VFront panel LED
LP_GOOD       inH133V_DLP Power Good
M10_RST       -A73V_D
M10_RX        -C23V_D
M10_TX        -B13V_D
MAX_IO1       inN83.3VI²C SCL in
MAX_IO10      -M103.3V
MAX_IO2       outN73.3VI²C SCL out
MAX_IO3       inM93.3VI²C SDA in
MAX_IO4       outM83.3VI²C SDA out
MAX_IO5       inM123.3VUser LED in
MAX_IO6       -M133.3V
MAX_IO7       -N93.3V
MAX_IO8       -N103.3V
MAX_IO9       -M113.3V
MIO22         outM3PS_1V8UART out
MIO23         inM2PS_1V8UART in
MIO24         -L3PS_1V8
MIO25         -H5PS_1V8
MR            outK103V_DSupervisor Reset out
N.C.-J53.3V
N.C.-J63.3V
N.C.-J73.3V
N.C.-J83.3V
N.C.-K53.3V
N.C.-K63.3V
N.C.-K73.3V
N.C.-K83.3V
N.C.-L43.3V
N.C.-L53.3V
N.C.-M53.3V
N.C.-M73.3V
N.C.-N43.3V
N.C.-N53.3V
N.C.-N63.3V
N.C.-L103.3V
N.C.-L113.3V
N.C.-N123.3V
nCONF         -E73V_D
nSTATUS       -C43V_D
ON_GT_L       outJ123V_DGT_L Power Enable
ON_GT_R       outK123V_DGT_R Power Enable
PG_DDR        inH83V_DDDR Power Good
PG_GT_L       inH93V_DGT_L Power Good
PG_GT_R       inG123V_DGT_R Power Good
PG_PL         inL133V_DPL Power Good
PG_PSGT       inK113V_DPSGT Power Good
PLL_RST       outK2PS_1V8PLL Chip Reset
PROG_B        outJ2PS_1V8FPGA PROG_B
PSON          -D63V_D
RP_SCL        -E13V_D
RP_SDI        -G43V_D
RP_SDO        -F43V_D
RP_SL         -F13V_D
RST           -B53V_D
RST_PRST      -A83V_D
RST_PRST_R    -B103V_D
RST_R         -D83V_D
SATA_SCL      -G23V_D
SATA_SDI      -F63V_D
SATA_SDO      -F53V_D
SATA_SL       -G13V_D
SMB_SCL       inoutE33V_D I²C SCL
SMB_SCL_R     outE43V_DI²C SCL Pullup Enable
SMB_SDA       inoutC13V_DI²C SDA
SMB_SDA_R     outD13V_DI²C SDA Pullup Enable
SRST_B        outH4PS_1V8FPGA SRST_B
SW4           inA53V_DDip Switch
SYSEN         -D73V_D
USR_BTN       inJ103V_DFront pannel panel button
WAKE          -A93V_D
WAKE_R        -A103V_D

...

System Controller provides control and status information for main power rails. By default all power rails are ON, the user can manipulate power using I²C interface, see  Memory map table.

Reset

System controller generate generates a reset pulse to supervisor chip U69 when front panel button S3 is pressed.

...

SC I/O #FunctionFPGA IO
IO1SCL OUTG18I²C SCL in
IO2SCL ING19I²C SCL out
IO3SDA OUTK18I²C SDA in
IO4SDA INH19I²C SDA out
IO5User LEDJ17Drive SC LED , if configured in "Control Register"
IO6-H17
IO7-H18
IO8-L18
IO9-L17
IO10-K17

...

AddressRegisterDescription
0Input Port 0

Power status register:

Bit 0 - LP_PGOOD

Bit 1 - PG_PL

Bit 2 - PG_PSGT

Bit 3 - PG_GT_L

Bit 4 - PG_GT_R

Bit 5 - PG_DDR

Bit 6 - Not Used "0"AVDD OV/UV

Bit 7 - Not Used "0"

1Input Port 1

FAN Status register

Bits 7:0 - FAN RPM/1000

(Nominal Sepa HFB44B-12A speed is 8000 RPM)

2Output Port 0

Control register 0

Bits 1:0 - LED Control (Default "01")

Bit 2 - SMB Strong Pull-Up Enable (Default "1")

Bit 3 - Enable DAC1 Power (Default "1")

Bit 4 - Enable DAC2 Power (Default "1")

Bit 5 - Enable DAC3 Power (Default "1")

Bit 6 - Enable DAC4 Power (Default "1")

Bit 7 - Enable FPD Power (Default "1")

3Output Port 1

Control register 1

Bit 0 - Enable LPD Power (Default "1")

Bit 1 - Enable DDR Power (Default "1")

Bit 2 - Enable PSGT Power (Default "1")

Bit 3 - Enable GT_L Power (Default "1")

Bit 4 - Enable GT_R Power (Default "1")

Bit 5 - Enable FAN Power (Default "1") (Works only if 4-wire FAN is used)

Bit 6 - Not usedEnable AVDD Power (Default "1")

Bit 7 - Not usedSystem reset (Default "0", Reset by rising edge)

LED Control

Bits [1:0]Mode
"00"LED4 is OFF
"01"LED4 is Power indicator
"10"LED4 is User LED (connected to IO5)
"11"LED4 is ON

...